This is a temporary, read-only recovery of the chessprogrammingwiki while a longer-term plan is worked out. Editing is not possible right now, but will be again soon.
Chess Programming Wiki All pages Other namespaces

ARM6

Home * Hardware * ARM6

ARM610 die 1ARM610 die 1

  1. Die shot of ARM610 microprocessor made by GEC Plessey Semiconductors, Photo by Pauli Rautakorpi, June 13, 2014↩︎

ARM6, (ARM610, ARM7)
a family of 32-bit RISC processors of the ARMv3 architecture released in early 1992 by Advanced RISC Machines Ltd, a company structured as a joint venture between Acorn Computers Ltd, Apple and VLSI Technology, which became ARM Ltd when its parent company, ARM Holdings, floated on the London Stock Exchange and NASDAQ in 1998 1. The ARM6 is instruction compatible to Acorn's ARM2, has a full 32-bit address bus, requiring an extra PSR register. The differences between ARM6 and the later ARM7 are that the latter has a hardware debug capability, the Thumb instruction set to support both 16-bit and 32-bit instruction formats and an enhanced multiplier 2.

Contents
  1. Computer Chess
  2. See also
  3. Manuals
  4. Publications
  5. External Links
  6. References

Computer Chess

The ARM6 and successors were used in various dedicated chess computers, notably the RISC 2500, Mephisto Montreux, TASC R30 and TASC R40.

See also

Manuals

Publications

References

Up one Level

  1. Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale - Wikipedia↩︎

  2. Michael J. C. Gordon (2004). Formal Specification and Verification of ARM6. Computer Laboratory, University of Cambridge, Final Report as pdf↩︎

  3. HOL (proof assistant) from Wikipedia↩︎

Categories: Die

What links here

Contributors: GerdIsenberg.