TSMC, the world’s leading semiconductor foundry, held its 2026 North America Technology Symposium on April 22 (local time). Under the theme “Expanding AI with Leadership Silicon,” the company unveiled several industry-leading semiconductor processes and packaging technologies. The highlight of the event was the first-ever revelation of the A13 process technology, designed to meet the extreme computing demands of next-generation AI, high-performance computing (HPC), and mobile applications.
“At TSMC, we understand our customers are always looking ahead to their next innovation, and they come to us for a reliable stream of new silicon technologies, like A13, meticulously engineered to be ready for high-volume production right when their visionary new designs demand them,” said TSMC Chairman and CEO Dr. C.C. Wei.
Following the announcement of A14 in 2025, TSMC officially introduced the A13 process technology this year. A13 is not just an extension of technology but a breakthrough in performance and area utilization:
Density Optimization: Compared to A14, A13 saves 6% in chip area.
High Compatibility: Design rules are fully backward-compatible with A14, allowing customers to quickly upgrade existing designs to the latest nanosheet transistor technology.
Production Timeline: A13 is expected to enter production in 2029.
Additionally, TSMC enhanced its A14 platform and previewed A12 technology. This process will utilize “Super Power Rail” technology for backside power delivery and is expected to enter production in 2029.
TSMC is also advancing its N2 platform with the introduction of N2U. Using design and technology co-optimization (DTCO), N2U achieves a 3-4% speed increase or an 8-10% power reduction compared to N2P, with a 2-3% increase in logic density. Leveraging the process maturity and high yield of the N2 platform, N2U serves as a balanced choice for AI, HPC, and mobile applications, with production expected to start in 2028.
To support the demand for higher computing power and memory within a single package, TSMC continues to expand its CoWoS® technology to integrate more silicon:
Ultra-Large CoWoS: The Company is now producing 5.5-reticle size CoWoS and planning for even larger versions. A 14-reticle size CoWoS, capable of integrating approximately 10 large compute dies and 20 HBM stacks, is slated for production in 2028. This will be followed by an expansion beyond 14 reticles in 2029.
SoW-X Technology: 40-reticle size SoW-X System-on-Wafer technology is also expected in 2029.
Co-Packaged Optics (CPO): The company’s Compact Universal Photonic Engine (TSMC-COUPE™) will reach a critical milestone, with a true CPO solution (COUPE on substrate) expected to begin production in 2026. By integrating the COUPE optical engine directly into the package, TSMC achieves 2X power efficiency and a 10X latency reduction compared to a pluggable version on the circuit board. The technology is featured in a 200Gbps micro-ring modulator, a highly compact and energy-efficient solution to move data between racks in data centers
TSMC will also launch TSMC-SoIC® 3D chip stacking on its most advanced platforms. A14-to-A14 SoIC is expected in 2029, offering 1.8x the die-to-die I/O density of N2-to-N2 SoIC technology to support higher data-transfer bandwidth.
For the automotive and robotics sectors, TSMC announced N2A, the first automotive process technology using nanosheet transistors, with AEC-Q100 validation expected in 2028. Meanwhile, the previously planned N3A enters production this year (2026), with over 10 customer products already planned.
Compared to N3A, N2A offers a 15-20% speed increase at the same power level. TSMC is also providing “Automotive Design Enablement” kits within the N2P Process Design Kit (PDK), allowing customers to begin designs early before N2A is fully validated.
In specialty technologies, TSMC is the first to bring high-voltage technology to the FinFET generation in 2026 with the N16HV process, primarily supporting display driver applications. For smartphone display drivers, N16HV increases gate density by 41% and reduces power consumption by 35% compared to N28HV. For near-eye displays, it reduces die area by 40% and power by over 20%, enhancing the usability of AR/VR devices such as smart glasses.
Chairman and CEO Dr. C.C. Wei emphasized that TSMC will continue to lead the industry in density, performance, and power efficiency. He stated: “TSMC’s advanced process technologies lead the industry in density, performance, and power efficiency, and we continually strive to make them even better for our customers’ future products, ensuring customers’ success as their most reliable technological partner.”
Headquartered in Hsinchu, Taiwan, TSMC operates across Asia, Europe, and North America. In 2025, the company provided 305 process technologies for 534 customers, producing 12,682 products. This North America Technology Symposium kicks off a series of global events where TSMC will continue to showcase its manufacturing and process innovation.
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