SYZYGY is great!
I realized that SYZYGY was a good choice for prototyping after successfully running a DDC receiver on an HF receiver pod with relatively little effort. Yes, SYZYGY is great!
Odyssey of Electronics and Computers
I realized that SYZYGY was a good choice for prototyping after successfully running a DDC receiver on an HF receiver pod with relatively little effort. Yes, SYZYGY is great!
Recently, I had to convert a large FPGA schematic symbol from KiCad into the OrCad XML library format. So, I delegated this task to my dear pal Claude, who accomplished it extremely well.
USB finally works. Now I’m able to connect an external USB hub to the socket and plug in thumb drives and USB hard disks. All works fine, except the USB-to-SATA converter, which is not soldered in yet. I saved that for the dessert, because I have other priorities. This is the ‘lsusb -t’ picture of a thumb drive plugged into the USB socket.
It’s USB show time! Xilinx documents suggest the USB3320 as a good USB PHY that works, and I’ve seen multiple development boards that use that chip. If it works for them, it will probably work for me, I thought. Despite being defined in Vivado hardware design, USB was not detected by the Linux kernel. Looking closely, I saw that a reference clock was ok, but there was no signal on the CLKOUT pin.
This is a short reminder to myself on how to configure the Petalinux for Zynq 7000. First, source the settings.sh from the Petalinux root folder. source ./settings.sh Create the project from Vivado hardware definintion export. It's a good idea to provide a complete path to the xsa file. petalinux-create project --template zynq --name nasrm-usb cd nasrm-usb petalinux-config --get-hw-description…
Today I was happily observing Linux boot messages on a NASR-M tty console. It was a major milestone in development. I decided to generate the PetaLinux image using the traditional workflow and leave the Yocto exploration for later. Sadly, good old PetaLinux tools will be deprecated in favor of Yocto in 2026.
Today is an important milestone in a board bring-up, as the DDR3 subsystem appears functional. I was able to run a Vivado bundled Zynq bare-metal DDR test with no errors. The test image was uploaded via JTAG and executed on a CPU core. That was the most important indication of a system's health to me. Even if other subsystems don’t work properly, I’ll be able to respin the board with minimal…
We’ve got a JTAG connection, ladies and gentlemen. My cheap Xilinx platform cable I ordered from AliExpress actually worked. I’ve got two of them. The first one didn’t work well and was pulling down the 3V3 power supply low, but the second one - bingo! The next step is a bare-metal CPU test. Lessons learned: before succumbing to despair and unmotivated aggression, check the bootstrap pins and set…
The LMK03328 clock driver is finally functional. Today, I was happily observing a sine-like signal at 33.33 MHz on the screen of my good old scope. I suppose it’s really a meander. Once I get a faster oscilloscope, I’ll be able to tell with confidence. What disappointed me was the low amplitude. The peak value was around 1.76 - 1.8V despite the 3.3V at the line #3 IO supply. The datasheet of…
Yesterday’s TCXO drama was resolved in a more elegant way than surgery. I have always been a fan of conservative treatment, and decided to try one last option before attempting rework. That option was an AC termination of the TCXO’s signal. The datasheet doesn’t explicitly mention single-ended AC termination of the reference input, so it’s kind of a gray area, but it’s perfectly fine for…