FPGA: Clocks, Timing, Metastability, and Clock Domain Crossing

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Introduction Every flip-flop inside the FPGA relies on a clock signal to determine when data should be sampled. Between two clock edges, electrical signals propagate through combinational logic, eventually arriving at the next register. If data arrives too late or changes too early, the receiving flip-flop may capture an incorrect value ( logic-0 or logic-1 ); this scenario is known as…

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