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6 min.RISC-V: Add test cases for vwmulu.vx reg overlapHEADtrunkmasterPan Li15-0/+276
6 min.RISC-V: Add test cases for vwmul.vx reg overlapPan Li15-0/+276
6 min.RISC-V: Add test cases for vwsubu.vx reg overlapPan Li15-0/+276
6 min.RISC-V: Add test cases for vwsub.vx reg overlapPan Li15-0/+276
6 min.RISC-V: Add test cases for vwaddu.vx reg overlapPan Li15-0/+276
6 min.RISC-V: Add test cases for vwadd.vx reg overlapPan Li16-0/+403
6 min.RISC-V: Allow RVV register overlap for vw{add,sub,mul}[u].vxPan Li1-9/+9
35 min.Daily bump.GCC Administrator4-1/+81
3 hours[PATCH] RISC-V: Improve slliw shifted bitfield split constraintsLuke Zhuang1-0/+2
5 hoursforwprop: Make hilo{0,1,2} an arrayAndrea Pinski1-22/+18
5 hoursmatch: Remove unused result captures from the widdening multiply matchesAndrea Pinski1-10/+11
5 hoursmatch: Use wi::to_wide moreAndrea Pinski1-5/+3
5 hoursmatch: Remove some INTEGER_CST checks there were already done (widdening mult...Andrea Pinski1-27/+27
5 hoursmatch: Remove `:c` in mul_cross_sumAndrea Pinski1-1/+1
5 hoursforwprop: Swap the comparisons for the match and the shift amount equalityAndrea Pinski1-4/+4
5 hoursmatch/forwprop: Simplify handling of cond_carry_addAndrea Pinski2-16/+9
7 hoursc++: modules vs typeid [PR124888]Jason Merrill5-27/+58
8 hours[committed] Fix minor arc testsuite regressionJeff Law1-1/+1
25 hoursDaily bump.GCC Administrator8-1/+528
26 hoursmatch: Use wi::to_wide instead of tree_to_uhwi in mul_hi/mul_lo [PR126958]Andrea Pinski1-4/+2
26 hoursmatch: Convert for mul_carry_low_sum and mul_carry_cross_sum is not optional ...Andrea Pinski1-2/+2
26 hoursmatch: simplify cond_carry_add and cond_carry_add_neg match by using `:c` [PR...Andrea Pinski1-6/+2
26 hoursmatch: Remove extra `#if GIMPLE` [PR126955]Andrea Pinski1-2/+0
26 hoursmatch: Use match to match mult for mul_ladder_sum1 [PR126954]Andrea Pinski1-11/+1
29 hoursmiddle-end: Add bitmask to default POLY_INT_CST ranges.Tamar Christina1-0/+2
31 hourslibstdc++: Ensure ./tzdata.zi is present in testcaseJonathan Wakely1-0/+3
32 hourscobol: Allow larger REDEFINES for -dialect ibm.James K. Lowden7-16/+28
32 hoursMAINTAINERS: Update my affiliation and DCO statusDavid Faust2-3/+7
33 hourslibcpp: Optimize AArch64 search_line_neonWilco Dijkstra1-83/+42
33 hoursRISC-V: Fix sub-Pmode index in vec_set/vec_extract [PR126873]Jin Ma2-2/+39
34 hoursAArch64: Add POLY_INT_CST bounds for SVE.Tamar Christina4-8/+218
34 hoursmiddle-end: Teach ranger about POLY_INT_CST ranges for VRP.Tamar Christina4-2/+108
34 hourstestsuite, x86, Darwin: Set non-pic option for ia32 tests that need it.Iain Sandoe28-0/+28
34 hoursc++, contracts: Use a tree-vec for contract specifiers.Iain Sandoe6-249/+241
34 hoursaarch64: Drop the duplicate vnarrowq mode attributeKyrylo Tkachov2-4/+1
34 hourslibstdc++: remove the gnu++11 in check performance scriptYuao Ma7-13/+8
35 hoursaarch64: Add `SME_MOP4` instrinsics and corresponding insnsKarl Meakin54-1/+3919
35 hoursaarch64: Add `SME_MOP4` predefinesKarl Meakin5-1/+15
35 hoursaarch64: Fix comments for register constraintsKarl Meakin1-5/+5
36 hoursImprove dom_oracle::clear performance.Andrew MacLeod2-5/+29
36 hoursImprove equiv_oracle::clear performance.Andrew MacLeod2-17/+65
36 hoursImprove infer::clear performance.Andrew MacLeod2-27/+32
37 hoursc++: improve SFINAE in lookup_destructorJason Merrill1-1/+3
37 hourstestsuite, X86: Fix missing asm macro in ms-sysv do-test.Iain Sandoe1-1/+1
37 hoursgimple-fold: fold fwrite of a single byte to fputcKyrylo Tkachov4-0/+123
38 hourstree: make TYPE_OVERFLOW_SANITIZED accept vector typesKyrylo Tkachov2-1/+13
39 hourstestsuite: Select SVE2 for the aarch64_sve2_hw probeKyrylo Tkachov1-0/+1
39 hourstree-optimization/126979 - fix SLP pattern representative checksRichard Biener1-53/+60
39 hourstree-optimization/126965 - limit recursive PRE expression generationRichard Biener2-3/+121
39 hoursRemove max_nunitsRichard Biener2-113/+21