Analog-to-digital converter

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AD570 8-bit successive-approximation analog-to-digital converter

AD570/AD571 silicon die

In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is a system that converts an analog signal, such as from fingers touching a touchscreen, sound entering a microphone, or light entering a digital camera, into a digital signal.

An ADC may also provide an isolated measurement, such as an electronic device that converts an analog input voltage or current to a digital number representing the magnitude of the voltage or current. Typically, the digital output is a two's complement binary number that is proportional to the input, but there are other possibilities.

There are several ADC architectures. Due to the complexity and the need for precisely matched components, all but the most specialized ADCs are implemented as integrated circuits (ICs). These typically take the form of metal–oxide–semiconductor (MOS) mixed-signal integrated circuit chips that integrate both analog and digital circuits.

A digital-to-analog converter (DAC) performs the reverse function; it converts a digital signal into an analog signal.

Characteristics

An ADC converts a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal. The conversion involves quantization of the input, so it necessarily introduces a small amount of quantization error. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input, and limiting the allowable bandwidth of the input signal.

The performance of an ADC is primarily characterized by its bandwidth, dynamic range and signal-to-noise and distortion ratio (SNDR). The bandwidth of an ADC is set largely by its sampling rate. The SNDR is influenced by many factors, including the resolution, noise floor, linearity and accuracy (how well the quantization levels match the true analog signal). Aliasing and jitter will degrade these specifications. The SNDR of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are, on average, not noise. An ideal ADC has an ENOB equal to its resolution. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then per the Nyquist–Shannon sampling theorem, near-perfect reconstruction is possible. The presence of quantization error limits the SNDR of even an ideal ADC. When the SNDR of the ADC exceeds that of the input signal, the effects of quantization error may be neglected, resulting in an essentially perfect digital representation of the bandlimited analog input signal.

Resolution

Fig. 1. An 8-level ADC coding scheme

The resolution of the converter indicates the number of different, i.e., discrete, values it can produce over the allowed range of analog input values. Thus, a particular resolution determines the magnitude of the quantization error and therefore determines the maximum possible signal-to-noise ratio for an ideal ADC without the use of oversampling. The input samples are usually stored electronically in binary form within the ADC, so the resolution is usually expressed in bits.

Resolution can also be defined electrically, and expressed in volts. The change in voltage required to guarantee a change in the output code level is called the least significant bit (LSB) voltage. The resolution Q of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of intervals:

$Q={\dfrac {E_{\mathrm {FSR} }}{2^{M}}},$

where M is the ADC's resolution in bits and E_FSR is the full-scale voltage range (also called 'span'). E_FSR is given by

$E_{\mathrm {FSR} }=V_{\mathrm {RefHi} }-V_{\mathrm {RefLow} },\,$

where V_RefHi and V_RefLow are the upper and lower extremes, respectively, of the voltages that can be coded.

Normally, the number of voltage intervals is given by

$N=2^{M},\,$

where M is the ADC's resolution in bits.

That is, one voltage interval is assigned in between two consecutive code levels.

Example:

• Coding scheme as in figure 1
• Full scale measurement range = 0 to 1 volt
• ADC resolution is 3 bits: 2³ = 8 quantization levels (codes)
• ADC voltage resolution, Q = 1 V / 8 = 0.125 V.

In many cases, the useful resolution of a converter is limited by the signal-to-noise ratio (SNR) and other errors in the overall system expressed as an ENOB.

Comparison of quantizing a sinusoid to 64 levels (6 bits) and 256 levels (8 bits). The additive noise created by 6-bit quantization is 12 dB greater than the noise created by 8-bit quantization. When the spectral distribution is flat, as in this example, the 12 dB difference manifests as a measurable difference in the noise floors.

Quantization error

Analog to digital conversion as shown with fig. 1 and fig. 2

Quantization error is introduced by the quantization inherent in an ideal ADC. It is a rounding error between the analog input voltage to the ADC and the output digitized value. The error is nonlinear and signal-dependent. In an ideal ADC, where the quantization error is uniformly distributed between −1⁄2 LSB and +1⁄2 LSB, and the signal has a uniform distribution covering all quantization levels, the signal-to-quantization-noise ratio (SQNR) is given by

$\mathrm {SQNR} =20\log _{10}({\dfrac {E_{\mathrm {FSR} }}{\tfrac {E_{\mathrm {FSR} }}{2^{M}}}})=20\log _{10}(2^{M})\approx 6.02\cdot M\ \mathrm {dB} \,\!$

where $M$ is the number of quantization bits. For example, for a 16-bit ADC, the quantization error is 96.3 dB below the maximum level.

Quantization error is distributed from DC to the Nyquist frequency. Consequently, if part of the ADC's bandwidth is not used, as is the case with oversampling, some of the quantization error will occur out-of-band, effectively improving the SQNR for the bandwidth in use. In an oversampled system, noise shaping can be used to further increase SQNR by forcing more quantization error out of band.

Dither

Main article: dither

In ADCs, performance can usually be improved using dither. This is a very small amount of random noise (e.g., white noise), which is added to the input before conversion. Its effect is to randomize the state of the LSB based on the signal. Rather than the signal simply getting cut off altogether at low levels, it extends the effective range of signals that the ADC can convert, at the expense of a slight increase in noise. Dither can only increase the resolution of a sampler. It cannot improve the linearity, and thus, accuracy does not necessarily improve.

Quantization distortion in an audio signal of very low level with respect to the bit depth of the ADC is correlated with the signal and sounds distorted and unpleasant. With dithering, the distortion is transformed into noise. The undistorted signal may be recovered accurately by averaging over time. Dithering is also used in integrating systems such as electricity meters. Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter.

Dither is often applied when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the eye looks far more realistic than the quantized image, which otherwise becomes banded. This analogous process may help to visualize the effect of dither on an analog audio signal that is converted to digital.

Accuracy

An ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear) non-linearity are intrinsic to any analog-to-digital conversion. These errors are measured in a unit called the least significant bit (LSB). In the above example of an 8-bit ADC, an error of one LSB is 1⁄256 of the full signal range, or about 0.4%.

Nonlinearity

All ADCs suffer from nonlinearity errors caused by their physical imperfections, causing their output to deviate from a linear function (or some other function, in the case of a deliberately nonlinear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing. Important parameters for linearity are integral nonlinearity and differential nonlinearity. These nonlinearities introduce distortion that can reduce the signal-to-noise ratio performance of the ADC and thus reduce its effective resolution.

Jitter

When digitizing a sine wave $x(t)=A\sin {(2\pi f_{0}t)}$, the use of a non-ideal sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time uncertainty due to clock jitter is $\Delta t$, the error caused by this phenomenon can be estimated as $E_{ap}\leq |x'(t)\Delta t|\leq 2A\pi f_{0}\Delta t$. This will result in additional recorded noise that will reduce the effective number of bits (ENOB) below that predicted by quantization error alone. The error is zero for DC, small at low frequencies, but significant with signals of high amplitude and high frequency. The effect of jitter on performance can be compared to quantization error: $\Delta t<{\frac {1}{2^{q}\pi f_{0}}}$, where q is the number of ADC bits.

Output size (bits)	Signal Frequency
	1 Hz	1 kHz	10 kHz	1 MHz	10 MHz	100 MHz	1 GHz
8	1,243 μs	1.24 μs	124 ns	1.24 ns	124 ps	12.4 ps	1.24 ps
10	311 μs	311 ns	31.1 ns	311 ps	31.1 ps	3.11 ps	0.31 ps
12	77.7 μs	77.7 ns	7.77 ns	77.7 ps	7.77 ps	0.78 ps	0.08 ps (77.7 fs)
14	19.4 μs	19.4 ns	1.94 ns	19.4 ps	1.94 ps	0.19 ps	0.02 ps (19.4 fs)
16	4.86 μs	4.86 ns	486 ps	4.86 ps	0.49 ps	0.05 ps (48.5 fs)	–
18	1.21 μs	1.21 ns	121 ps	1.21 ps	0.12 ps	–	–
20	304 ns	304 ps	30.4 ps	0.30 ps (303.56 fs)	0.03 ps (30.3 fs)	–	–
24	18.9 ns	18.9 ps	1.89 ps	0.019 ps (18.9 fs)	-	–	–

Clock jitter is caused by phase noise. The resolution of ADCs with a digitization bandwidth between 1 MHz and 1 GHz is limited by jitter. For lower bandwidth conversions such as when sampling audio signals at 44.1 kHz, clock jitter has a less significant impact on performance.

Sampling rate

Main article: Sampling rate

An analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled and then the original signal can be reproduced from the discrete-time values by a reconstruction filter. The Nyquist–Shannon sampling theorem implies that a faithful reproduction of the original signal is only possible if the sampling rate is higher than twice the highest frequency of the signal.

Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task—in most cases by using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.

Aliasing

Main article: Aliasing

An ADC works by sampling the value of the input at discrete intervals in time. Provided that the input is sampled above the Nyquist rate, defined as twice the highest frequency of interest, then all frequencies in the signal can be reconstructed. If frequencies above half the Nyquist rate are sampled, they are incorrectly detected as lower frequencies, a process referred to as aliasing. Aliasing occurs because instantaneously sampling a function at two or fewer times per cycle results in missed cycles, and therefore, the appearance of an incorrectly lower frequency. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz sine wave.

To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signals with higher frequency content. In applications where protection against aliasing is essential, oversampling may be used to greatly reduce or even eliminate it.

Although aliasing in most systems is unwanted, it can be exploited to provide simultaneous down-mixing of a band-limited high-frequency signal (see undersampling and frequency mixer). The alias is effectively the lower heterodyne of the signal frequency and sampling frequency.

Oversampling

Main article: Oversampling

For economy, signals are often sampled at the minimum rate required, with the result that the quantization error introduced is white noise spread over the whole passband of the converter. If a signal is sampled at a rate much higher than the Nyquist rate and then digitally filtered to limit it to the signal bandwidth produces the following advantages:

• Oversampling can make it easier to realize analog anti-aliasing filters
• Improved audio bit depth
• Reduced noise, especially when noise shaping is employed in addition to oversampling.

Oversampling is typically used in audio frequency ADCs where the required sampling rate (typically 44.1 or 48 kHz) is very low compared to the clock speed of typical transistor circuits (>1 MHz). In this case, the performance of the ADC can be greatly increased at little or no cost. Furthermore, as any aliased signals are also typically out of band, aliasing can often be eliminated using very low-cost filters.

Common features

Many ADCs send their output data one bit at a time over a serial interface, thus using fewer signals (and device pins) than would be required for parallel data transmission. Some integrated circuit ADCs provide multiple inputs that can be individually selected for digitization, usually through an analog multiplexer, as well as functions such as sample and hold, programmable gain, and differential inputs that allow measurement of the voltage difference between two inputs.

Types

There are several common ways of implementing an electronic ADC.

Flash

Main article: Flash ADC

Flash ADC

A flash ADC, also known as a parallel search ADC, employs a bank of voltage comparators sampling the input signal in parallel, each with a different voltage threshold. The circuit consists of a resistive divider network, an array of voltage comparators and a priority encoder. Each node of the resistive divider provides a voltage threshold for one comparator. The comparator outputs are applied to a priority encoder, which generates a binary number proportional to the input voltage.

Flash ADCs have a large die size and high power dissipation. They are used in a variety of applications, including video, wideband communications, and for digitizing other fast signals.

The circuit performs high speed conversions as the voltage comparators operate concurrently, in parallel. Typical conversion time is 100 ns or less. For each additional output bit, the number of comparators almost doubles, the priority encoder becomes more complex, and power doubles, but conversion time does not significantly increase.

Successive approximation

A successive-approximation ADC uses a voltage comparator, digital-to-analog converter (DAC), and sequential logic to digitize via a binary search, producing one bit of the ADC output word per clock cycle. The sequential logic, known as the successive approximation register (SAR), is a finite state machine that embodies the binary search algorithm. The binary word issued by the SAR serves as both ADC output and DAC control input.

The DAC output voltage range defines the allowed input voltage range. In the first clock cycle, the most significant SAR bit (MSB) is set, thus programming the DAC to the midpoint of the voltage range as a first approximation. At each successive clock cycle, the input and DAC voltages are compared, the SAR bit is cleared or left set depending on the result of this comparison (thus resolving the output bit and narrowing the voltage range for the next comparison), and the next (less significant) SAR bit is set for the next approximation. At each step in this process, the approximation value stored in the SAR resolves one ADC output bit and narrows the remaining voltage search range by half. The conversion is completed when the SAR least significant bit (LSB) has been resolved.

Ramp-compare

A ramp-compare ADC uses a sawtooth wave generator, voltage comparator, and digital counter to perform analog-to-digital conversions. It produces a sawtooth signal whose voltage linearly ramps up or down from zero volts, which is applied to one input of the comparator. The analog input voltage is applied to the other comparator input.

Various techniques are used to generate the sawtooth wave. For example, nonlinear ramps can be produced by a microcontroller in conjunction with a resistor and capacitor. When using an analog integrator to generate the ramp, the ramp duration may be sensitive to temperature. To avoid this, a DAC may be used to generate the ramp, with DAC inputs driven by the counter as shown in the example circuit below.

Upon start of conversion, a voltage ramp begins, the count is zeroed and the counter starts counting constant-frequency clock pulses. When the ramp reaches the input voltage, the comparator output changes state. This state change causes the accumulated count to be copied to a holding register, which serves as the ADC output. The ADC output value is proportional to the input voltage. The holding register retains and issues the ADC data while the next conversion is in progress.

Dual-slope integrating ADC

Voltage waveform at the integrator output in a dual-slope ADC, showing ramp-up period T and ramp-down period t_x

An integrating ADC (also dual-slope or multi-slope ADC) uses an integrator, voltage comparator, counter and control logic to perform analog-to-digital conversions. The buffered input voltage is applied to the integrator and the integrator output voltage is allowed to ramp up for a fixed time (the run-up period). A reference voltage of opposite polarity is then applied to the integrator and the integrator output is allowed to ramp down until it returns to zero (the run-down period). The periods are measured in units of the converter's clock period.

The input voltage is computed as a function of the reference voltage, run-up period, and run-down period. Longer integration times provide higher resolution, but the conversion time doubles for each additional bit of resolution, and consequently this type of ADC is well suited for measuring slowly varying signals such as thermocouples and weighing scales. Converters of this type (or related variations) are commonly used in digital voltmeters.

Tracking

A tracking ADC has an up-down counter that feeds a DAC. The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output matches the input signal and number is read from the counter.

Tracking converters have very wide ranges and high resolution, but the conversion time is dependent on the input signal behavior, though it will always have a guaranteed worst-case. Tracking converters are often very good choices to read real-world signals as most signals from physical systems do not change abruptly. Some converters combine the tracking and successive approximation approaches; this works especially well when high-frequency components of the input signal are known to be small in magnitude.

Pipelined

A pipelined ADC (also called subranging quantizer) uses two or more conversion steps. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a DAC. This difference is then converted more precisely, and the results are combined in the last step. This can be considered a refinement of the successive-approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and can be implemented efficiently.

Delta-sigma

Main article: Delta-sigma modulation

A delta-sigma ADC (also known as a sigma-delta ADC) is based on a negative feedback loop with an analog filter and low resolution (often 1 bit) but high sampling rate ADC and DAC. The feedback loop continuously corrects accumulated quantization errors and performs noise shaping: quantization noise is reduced in the low frequencies of interest, but is increased in higher frequencies. Those higher frequencies may then be removed by a downsampling digital filter, which also converts the data stream from that high sampling rate with low bit depth to a lower rate with higher bit depth.

Voltage-to-frequency

A voltage-to-frequency (V/F) ADC, also known as an intermediate frequency modulator (FM) ADC, employs a voltage-to-frequency converter (VFC) in conjunction with a frequency counter to perform analog-to-digital conversions. The analog input voltage serves as a control input to the VFC, which in turn outputs a periodic signal with frequency proportional to the input voltage. The frequency counter measures the VFC output frequency, issuing the measurement as a binary value (the ADC output) which is proportional to the frequency, and thus also proportional to the analog input voltage.

Each measurement made by the frequency counter occurs over the course of an interval known as the gate time. Since the analog input voltage, and consequently the VFC frequency, can change during the gate time, the measurement is effectively an integrating conversion, with integration time equal to the gate time. Longer gate times result in slower conversions and higher measurement resolution, whereas shorter gate times result in faster conversions and lower resolution.

The VFC and frequency counter communicate via a single digital signal. Consequently, they can easily be distantly separated, and the VFC output signal may be conveyed through an opto-isolator or wirelessly, thus facilitating galvanic isolation between the analog input and ADC output circuits. Such ADCs are widely used for this purpose, and were once the most popular way to digitize remote analog sensors.

Wilkinson

A Wilkinson ADC performs analog-to-digital conversions by storing the voltage to be measured on a capacitor, and then discharging the capacitor at a constant rate while measuring the discharge time with a binary counter. When the ADC is idling (not digitizing), the analog input voltage is electrically connected to the capacitor, thus causing the capacitor voltage to track the input voltage, and counting is disabled. Upon start of conversion, the capacitor is disconnected from the analog input — leaving the voltage to be converted stored on the capacitor — and the counter is zeroed. The capacitor is then connected to a constant current source and the counter is enabled. The current source discharges the capacitor at a constant rate, resulting in a negative-sloped, linear voltage ramp whose duration is proportional to the sample voltage. While the voltage is ramping down, the counter counts constant-frequency clock pulses. When the ramp reaches zero volts, the conversion has finished and the converter returns to idle mode. The binary number output by the halted counter is a measure of the ramp time, and thus is proportional to the measured voltage.

The Wilkinson ADC was designed by Denys Wilkinson in 1950. The conversion time is inversely proportional to the clock frequency and proportional to the input amplitude. Due to the latter, higher voltages result in longer conversion times.

Wilkinson converters were widely used in multichannel analyzers for nuclear spectroscopy through the 1960s and 1970s. In such applications, a peak detector is typically used to detect voltage pulses at the analog input. The peak detector starts an ADC conversion upon detecting the peak of an input pulse, thus leaving the peak voltage stored on the capacitor, and consequently the resulting ADC data is a measure of the peak input voltage.

Applications

Time-stretch

A time-stretch analog-to-digital converter (TS-ADC) digitizes a high-bandwidth analog signal by time-stretching the signal prior to digitization. It commonly uses a photonic preprocessor to time-stretch the signal, which effectively slows the signal down in time and compresses its bandwidth. As a result, an ADC which is too slow to capture the original signal can capture the stretched signal.

To allow continuous capture of the signal, the front end divides the stretched signal into multiple segments so that each segment cay be digitized by a separate ADC. A digital signal processor rearranges the samples and removes any distortions added by the preprocessor to yield the binary data that accurately represents the original analog signal.

Interleaved ADCs

Two or more ADCs may be interleaved to increase the sampling rate beyond that of the individual ADCs and reduce the signal-to-noise ratio. In a time-interleaved ADC consisting of M ADCs, the sampling clock is uniquely phase-shifted for each ADC so that their sampling times are uniformly distributed over a clock period, thus increasing their combined sample rate to M times the sample rate of each individual ADC. In practice, individual ADC differences degrade the overall performance of such circuits, reducing the spurious-free dynamic range (SFDR). However, techniques exist to correct for these mismatch errors.

Sliding scale method

In 1963, the sliding scale method was introduced as a way to reduce differential nonlinearity in ADCs used in radiation detection systems. In such applications, the ADC samples are accumulated into histogram "bins" representing measured particle energies. If some samples correspond to slightly wider or narrower input voltage ranges than others, the resulting bins are uneven, resulting in visible structure in what should be smooth spectra.

The method works by adding a known, random analog offset to the input before conversion and subtracting the corresponding digital value from the resulting ADC sample. Although the final numerical result is unchanged, each conversion effectively occurs at a different position along the ADC transfer characteristic. When many samples are accumulated, the output codes represent an average over several adjacent code widths, reducing the impact of differential nonlinearity.

Measuring physical values other than voltage

Analog-to-digital converters are often used to acquire data from physical processes that do not directly produce voltages. Example of this include:

• Capacitive sensing converts from the analog physical quantity of a capacitance. That capacitance could be a proxy for some other physical quantity, such as the distance some metal object is from a metal sensing plate, or the amount of water in a tank, or the permittivity of a dielectric material.
• Sensors in general that don't directly produce a voltage may indirectly produce a voltage or, through other ways, be converted into a digital value.
  • Resistive output (e.g., from a potentiometer or a force-sensing resistor) can be made into a voltage by sending a known current through it, or can be made into an RC charging time measurement, to produce a digital result.

Measuring analog resistance or capacitance

One way to measure resistance or capacitance is to use it in a series RC circuit and measure the time required to charge the capacitance. Knowing the starting and ending capacitor voltages, supply voltage, and capacitance or resistance, the unknown value can be determined by solving for it via the capacitor charging equation:

$$V_{\text{capacitor}}(t)=V_{\text{supply}}\left(1-e^{-{\frac {t}{RC}}}\right)$$ The accuracy of this method is affected by a number of factors, including significant variation in resolution due to the nonlinear charging function.

Music recording

4-channel stereo multiplexed analog-to-digital converter WM8775SEDS made by Wolfson Microelectronics placed on an X-Fi Fatal1ty Pro sound card

Analog-to-digital converters are widely used to convert analog music signals to digital data streams, and are integral to modern music reproduction technology and digital audio workstation-based sound recording. In many cases they are used to create pulse-code modulation (PCM) data streams that are stored as digital music files on compact discs and other storage media. ADCs utilized in music typically sample at rates up to 192 kilohertz. Many recording studios record in 24-bit 96 kHz pulse-code modulation (PCM) format and then downsample and dither the signal for Compact Disc Digital Audio production (44.1 kHz) or to 48 kHz for radio and television broadcast applications.

Digital signal processing

ADCs are required in digital signal processing systems that process, store, or transport virtually any analog signal in digital form. TV tuner cards, for example, use fast video analog-to-digital converters. Slow on-chip 8-, 10-, 12-, or 16-bit analog-to-digital converters are common in microcontrollers. Digital storage oscilloscopes need very fast analog-to-digital converters, also crucial for software-defined radio and their new applications.

Scientific instruments

INTERSIL ICL7107. 3.5 digit (i.e., conversion from analog to a numeric range of 0 to 1999 vs. 3 digit range of 0 to 999, typically used in meters, counters, etc.) single-chip A/D converter

Digital imaging systems commonly use analog-to-digital converters for digitizing pixels. Some radar systems use analog-to-digital converters to convert signal strength to digital values for subsequent signal processing. Many other in situ and remote sensing systems commonly use analogous technology.

Many sensors in scientific instruments produce an analog signal; temperature, pressure, pH, light intensity etc. All these signals can be amplified and fed to an ADC to produce a digital representation.

Displays

Flat-panel displays are inherently digital and need an ADC to process an analog signal such as composite or VGA.

Electrical symbol

Testing

Testing an analog-to-digital converter requires an analog input source and hardware to send control signals and capture digital data output. Some ADCs also require an accurate source of reference signal.

The key parameters to test an ADC are:

1. DC offset error
2. DC gain error
3. signal-to-noise ratio (SNR)
4. Total harmonic distortion (THD)
5. Integral nonlinearity (INL)
6. Differential nonlinearity (DNL)
7. Spurious free dynamic range
8. Power dissipation

See also

• Adaptive predictive coding, a type of ADC in which the value of the signal is predicted by a linear function
• Audio codec
• Beta encoder
• Integral linearity
• Modem
• Time-to-digital converter
• Sample abundance

References

• Knoll, Glenn F. (1989). Radiation Detection and Measurement (2nd ed.). New York: John Wiley & Sons. ISBN 978-0-471-81504-4.
• Nicholson, P. W. (1974). Nuclear Electronics. New York: John Wiley & Sons. pp. 315–316. ISBN 978-0-471-63697-7.

Further reading

• Ortmanns, Maurits; Kaesser, Paul; Wagner, Johannes (2026). Incremental Delta-Sigma ADCs. Springer Cham. ISBN 978-3-032-09468-1.
• Allen, Phillip E.; Holberg, Douglas R. (2002). CMOS Analog Circuit Design. ISBN 978-0-19-511644-1.
• Fraden, Jacob (2010). Handbook of Modern Sensors: Physics, Designs, and Applications. Springer. ISBN 978-1-4419-6465-6.
• Kester, Walt, ed. (2005). The Data Conversion Handbook. Elsevier: Newnes. ISBN 0-7506-7841-0.{{cite book}}: CS1 maint: publisher location (link)
• Johns, David; Martin, Ken (1997). Analog Integrated Circuit Design. Wiley. ISBN 978-0-471-14448-9.
• Liu, Mingliang (2006). Demystifying Switched-Capacitor Circuits. Newnes. ISBN 978-0-7506-7907-7.
• Norsworthy, Steven R.; Schreier, Richard; Temes, Gabor C. (1997). Delta-Sigma Data Converters. IEEE Press. ISBN 978-0-7803-1045-2.
• Razavi, Behzad (1995). Principles of Data Conversion System Design. New York, NY: IEEE Press. ISBN 978-0-7803-1093-3.
• Ndjountche, Tertulien (May 24, 2011). CMOS Analog Integrated Circuits: High-Speed and Power-Efficient Design. Boca Raton, FL: CRC Press. ISBN 978-1-4398-5491-4.
• Staller, Len (February 24, 2005). "Understanding analog to digital converter specifications". Embedded Systems Design.
• Walden, R. H. (1999). "Analog-to-digital converter survey and analysis". IEEE Journal on Selected Areas in Communications. 17 (4): 539–550. doi:10.1109/49.761034.

External links

• An Introduction to Delta Sigma Converters A very nice overview of Delta-Sigma converter theory.
• Digital Dynamic Analysis of A/D Conversion Systems through Evaluation Software based on FFT/DFT Analysis RF Expo East, 1987
• Which ADC Architecture Is Right for Your Application? article by Walt Kester
• ADC and DAC Glossary at the Wayback Machine (archived 2009-11-24) Defines commonly used technical terms
• Introduction to ADC in AVR – Analog to digital conversion with Atmel microcontrollers
• Signal processing and system aspects of time-interleaved ADCs
• MATLAB Simulink model of a simple ramp ADC
• "Principles of Data Acquisition and Conversion" (PDF). ti.com. Texas Instruments. April 2015 [January 1994]. Retrieved October 29, 2024.