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Zachary Yedidia's blog

Recent content on Zachary Yedidia's blog

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Visualizing the ARM64 Instruction Set

Introduction Lately I’ve been doing a lot of work with the ARM64 instruction set, and I thought it would be fun to try to visualize it. ARM64 encodes every instruction as a 32-bit integer, so one way to visualize the instruction set is by plotting the instructions along a space-filling curve, such as a Hilbert curve1, and coloring them according to their instruction class (i.e., general,…

Unsafe transmute implemented in Safe Rust

I came across this issue on the Rust issue tracker recently: https://github.com/rust-lang/rust/issues/57893. One of the GitHub comments shows how you can abuse this bug to write a transmute1 function without the use of unsafe (and then you can obviously use this to cause undefined behavior in Safe Rust programs). trait Object<U> { type Output; } impl<T: ?Sized, U> Object<U> for T { type Output =…

Incremental D Compilation with Knit

A new feature in Knit I&rsquo;ve been writing a build tool called Knit (I&rsquo;ve written a blog post about it here). In Knit v1.1.0 there is a new feature I&rsquo;m calling &ldquo;dynamic task elision&rdquo;, which allows Knit to skip a build step if, at the time when it tries to run the task, it can determine that out-of-date prerequisites that got rebuilt ended up not changing anything. This…

Knit: making a better Make

This article is about a new build tool I&rsquo;ve been working on called Knit. Check it out on GitHub! What&rsquo;s wrong with Make? This might be surprising but I actually like Make overall. It has a concise syntax for declaring dependencies, and it doesn&rsquo;t make any assumptions about the programs I am building. These are the two biggest factors I consider when looking for a replacement, and…

Bare-metal development on the VisionFive 2 with D

This is a follow-up to my previous post about writing bare-metal RISC-V programs using D. This time we&rsquo;ll get our code running on actual hardware. We&rsquo;ll be using the VisionFive 2 board, a recently released RISC-V SBC with 4 application cores (SiFive U74) clocked at a maximum of 1.5 GHz1 and 1 monitor core (SiFive S7). The main difference between the U74 cores and the S7 core is that…

Writing a bare-metal RISC-V application in D

This post will show you how to use D to write a bare-metal &ldquo;Hello world&rdquo; program that targets the RISC-V QEMU simulator. In a future blog post (now available) we&rsquo;ll build on this to target actual hardware: the VisionFive 2 SBC. See blog-code for the final code from this post. For a more complex example, see Multiplix, an operating system I am developing that runs on the…

Starting a blog

Hi there! I&rsquo;ve set up a blog. I&rsquo;ll probably write about things I&rsquo;m working on or find interesting. Lately that includes things such as OS development, the D programming language, symbolic execution, hardware design and verification (with Chisel), build systems, text editors, and more. Stay tuned!