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AI infrastructure research across photonics, memory, interconnects, power, and packaging. Engineering depth translated for professionals and investors.

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How Coherent Can Earn Investor Confidence

Bridging The Gap Between Market Skepticism And Industry Reality, And What To Watch For Next.

OCP APAC: Copper vs. Optics Contradictions

Everybody is scrambling for ways to hook up stuff.

[Post-$] Astera Labs is a Switch Company in Connectivity Clothing

ALAB is a copper play with high growth switches, CXL opportunities and optics dreams.

Astera Labs: From the Tray to the Rack, and What Comes After

PCIe Switches, AWS Trainium, NVLink Fusion, and the UALink Future

The AI Trade Burned Down: Let Round 2 Begin

With more sanity this time...

HBM is the Ugly Baby: What Now?

Innovations in memory architecture will save the day.

Lasers for CPO/NPO: Part 2 – Lumentum’s Technology and Moat

How JDSU/Lumentum engineered their UHP laser, where the competition stands, and how its all about "is it good enough?"

Lasers for CPO/NPO: Part 1 – The InP DFB Laser

How an InP DFB laser works, and the four physical walls that make high power hard.

Kyber Midplane Design, Making NVL72x2 Work, and All Roads Lead to CPO

An engineering-first read of the supposed Kyber delay, why NVL72x2 was the "odd" duck nobody wanted, how to actually deploy it, and why CPO is the ultimate answer for large world sizes.

Qualcomm's High Bandwidth Compute and the Packaging Problem It Moved

HBC stacking DRAM on the compute die increases memory bandwidth and skips CoWoS. The packaging problem does not go away, it shifts to 3D.