DDR Compliance Simulation in Seconds, Not Days

On this episode of the Altium OnTrack Podcast, host Zach Peterson talks with Ben Dannan, founder of Signal Edge Solutions and DesignCon Engineer of the Year, and Tyler Huddleston, SI/PI engineer, about a problem every high-speed designer knows too well: DDR compliance simulation that can take 24 hours to several days per interface. They walk through why the traditional Keysight ADS Memory Designer…