Acceleration with HLS - Load, Compute, Store

In my daily work on FPGAs for the CMS Level 1 Trigger we usually are not limited by I/O into the devices. We work with boards, like the Serenity and APx, which can support 4-5 Tb/s input on around 100 optical fibres with very low latency - 100 ns or so for a hop from one board to the next. This is very convenient for designing algorithms, since often all (or at least many) of the inputs can be…