Debugging VexRiscv Over a JTAG Tunnel with OpenOCD

Wouldn’t it be nice if the same JTAG cable used to configure a FPGA could also debug a RISC-V core implemented in the fabric? Turns out, it’s possible! For a new project using a VexRiscv core to control a few things, I wanted to try tunneled JTAG access. Also, I may have forgotten to add a separate JTAG header on my board design… Anyway, I’ll share how to configure VexRiscv and OpenOCD to use one…