How to use $readmemh correctly

What? $readmemh is a Verilog directive that allows you to initialize an array. It works differently in simulation compared to synthesis. In simulation, this directive behaves as a &ldquo;read file into array&rdquo;. In synthesis, this directive behaves as a repository of initial values for, say, block RAM. While the purpose of the directive is documented every which way, the correct usage of the…