Running Vivado in an LXC Container
Running Vivado in an LXC container for fun and profit
Three-Speed Logic
Latest posts
C/RTL Cosimulation with Vivado and Python
A method to cosimulate C and RTL code under Python control
XSim's New AXI Analyzer
Xilinx's simulator can intelligently display AXI in block designs. We want that in RTL too.
Designing CIC Compensation Filters
Designing CIC compensation filters without MATLAB
Tworoutines in Python
An interesting, and possibly doomed, method of combining async and synchronous Python code
Exploring the Orbital Radiation Environment with Python
A look through the GOES satellite data archive
ICEboard: an FPGA / ARM Motherboard
The ICEboard is a fully custom FPGA / ARM motherboard hosting two high-pin-count (HPC) FPGA Mezzanine (FMC) slots. The ICEboard, revision 2. The two red mezzanines host high-speed (gigasample per second) ADCs for the CHIME experiment. The motherboard hosts an FPGA and ARM for processing elements, and a variety of high-speed …