I’m looking forward to speaking at DVClub this Thursday. If you are in Austin you can register for free below. The topic of my talk will be a paper I presented at DVCon 2021 “Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods”. If you haven’t been to a DVClub event before, you will enjoy it! There is typically a catered lunch and one or two guest speakers.…
I have been a user of the Tentacle Sync E timecode generator for years now and I love the product. It does exactly what I need and I never had to sync the audio and video in my recordings again. But the mount to the camera was always something I never liked. So I decided to design and build my own.
On Nov 12th I gave a talk to the IEEE Twin Cities Consulting Network on “Better Video Conferencing” with my thoughts and gear I use for video conferencing. Below are the slides. The talk was stories and background on the choices I made in putting together the setup.
On 10/26/2020 I gave a short update to a presentation I made in March 2019 on the same topic. Followed by a question and answer for the IEEE Coulee Subsection with the slides (PDF) below.
The IEEE Twin Cities Section and MFESTS (Minnesota Federation of Engineering, Science and Technology Societies) is having their annual banquet this Saturday, Feb 23rd in St. Paul at 5:30 pm. You should come! Imagine saying to your significant other tonight: “I want to dress up like a suave gentleman / sophisticated lady and bring you to an event at the beautiful James B. Woulfe Alumni Hall on the…
I had given a talk in September, 2018 titled “Owning a Tesla: Going Electric” for the IEEE Twin Cities Section on my experiences as a Tesla owner with my Model S. I’m excited to share that I will be giving an updated version of that talk tomorrow, Monday, January 28th 2019, in Rochester, Minnesota for the IEEE Southern Minnesota Section . The event is free and open to the public. There may even be…
A few years ago I wrote a paper for the Design and Verification Conference inspired by the book “Head First Design Patterns” by Robson and Freeman. “ Head First Design Patterns” is an excellent way to learn about Design Patterns. I liked the style of the book, which was lighthearted and written in a conversational tone. It made learning about Design Patterns actually fun!
I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is: "Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation" Abstract Constrained Random simulation is so critical to modern verification environments that it is a major component of…
I saw that my hosting provider now supports SSL which is a nice upgrade. As a visitor you get encrypted and possibly faster response time since it uses HTTP2 style communication too.
I'm honored to share that my paper: "Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012" was awarded Best Paper at the Design and Verification Conference (DVCon) 2016. The link to the final paper is now available.
The SystemVerilog bind command allows for adding new functionality to a module. Typically, it is used to add new checking to a RTL block. I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used. When you think about what bind is actually doing it starts to make sense.
I was working on a testbench and made a mistake. I saw a SystemVerilog code construct I wasn't used to and "corrected" it. I ended up disconnecting a port that was implicitly connected. There is already an authorative paper on this subject "SystemVerilog Implicit Port Connections by Cliff Cummings " which is very good.
UVM has a powerful display capability baked into it from the uvm_report_object. Using it allows for capabilities such as: getting the debug info you want out of components without being blinded by everything silencing messages you don't want to see breaking out detailed logs into seperate files to not clutter up the simulation logs for everyone else I put together a reference environment on GitHub…
DVCon 2015 had a paper by John Dickol titled "SystemVerilog Constraint Layering via Reusable Randomization Policy Classes" that described how SystemVerilog constraints could be layered onto an object. The previous method was to do a factory override or extend the class to get this type of behavior. I loved the idea. It solves a lot of problems such as having to create and manage extended classes…
I have a paper and a presentation session slot at DVCon 2015 (Design and Verification Conference) in San Jose, California. The title of the paper is "Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches" and I am excited to share it with the verification community. It will be presented on Wednesday, March 4th in the Monterey/Carmel hall in the…
The next Design pattern I ported to SystemVerilog is the Observer Pattern below. See the Strategy Pattern in SystemVerilog for more background on this mini project. Observer Pattern in SystemVerilog on GitHub
Chris Drake's blog Fuzzy Logic had a particular post titled Verilog Flip-Flop Macros which I thought was really good. It deals with creating an abstraction of a flip-flop in SystemVerilog. I had to try out his example code myself to verify the performance differences he experienced.
I had watched a wonderful video series of Object Oriented Design Patterns on Lynda.com called "Foundations of Programming: Design Patterns" by Elisabeth Robinson and Eric Freeman. In their series, they go through some of the ideas in "Design Patterns" and have very concise code examples that illustrate specific Design Patterns.
If you are using a graphical version of Emacs, you sometimes need to make things bigger or smaller depending on what you want to see or show to someone at your desk. There are two ways to to this.
There were two early articles on this blog that I wrote dealing with merging SystemVerilog covergroups: * Merging SystemVerilog Covergroups with Examples * Merging SystemVerilog Covergroups for Efficiency The two posts were rewritten and are now available in Mentor's "Verification Horizons" June 2014 quarterly publication under the title " Merging SystemVerilog Covergroups by Example". I'm happy…