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The 286's internal registers

The LOADALL structure as described by Intel is this: Physical Address (Hex) Associated CPU Register 800-805 None 806-807 MSW 808-815 None 816-817 TR 818-819 Flag word 81A-81B IP 81C-81D LDT 81E-81F DS 820-821 SS 822-823 CS 824-825 ES 826-827 DI 828-829 SI 82A-82B BP 82C-82D SP 82E-82F BX 830-831 DX 832-833 CX 834-835 AX 836-83B ES descriptor cache 83C-841 CS descriptor cache 842-847 SS descriptor…

Intel 286 secrets: ICE mode and F1 0F 04

With some recent interest in undocumented opcodes and microcode on modern Intel chips, I decided to do a proper writeup on what I found out while researching and playing around with the venerable 80286 ("Beige Unlock"?). Follow-up here ICE mode The documentation for the '286s LOADALL instruction - which Intel only made available under NDA back in the day - briefly mentions how it is used during…