# newest submissions : FPGA A subreddit for programmable hardware, including topics such as: \* FPGA \* CPLD \* Verilog \* VHDL Page: Feed: --- ## [Which would you guys pick?](https://www.reddit.com/r/FPGA/comments/1w19q35/which_would_you_guys_pick/) _2026-08-29 · /u/BronzeGstring_ Recently was fortunate enough to get 2 offers for FPGA engineer company A : 135k base Fully assisted relocation 15k sign on company B: 90k base 4.5k relo 6k sign on now I know what you’re thinking , clearly company A right? But it’s in SoCal and company B is in the Dallas area where rent is like a grand and no income taxes both are the same kind of role but company A would start me at Ivl 2 (i‘m a… ## [I made a website to practice and learn VHDL and SystemVerilog](https://www.reddit.com/r/FPGA/comments/1w0xd0c/i_made_a_website_to_practice_and_learn_vhdl_and/) _2026-08-28 · /u/Delicious-Charge9693_ I built this tool for myself, so that I could practice and solve challenges without having to set up an entire toolchain on my computer. The entire thing just work in browser. www.risingedge.pro I'd like you guys to try it out and see if you can solve the Practice challenges - there are over 50 at different difficulty levels, and all of them are entirely free of charge (no account required either… ## [smart contracts accelerator](https://www.reddit.com/r/FPGA/comments/1w0sba3/smart_contracts_accelerator/) _2026-08-28 · /u/Imaginary\_Cat1664_ Hey, Does anybody know whether HFT/Crypto companies use hardware accelerators for ethereum smart contracts? I'm talking mostly about fpgas / asics based opcode sequence paths? I guess if they did -\> they would offload the entire smart contract / a bunch of them onto the FPGA to ammortise the latency cost of data transfer from cpu to the chip, but at that point you'd be better off having the entire… ## [synthpilot ANTI VIRUS alarm deleting the exe files](https://www.reddit.com/r/FPGA/comments/1w0p4y2/synthpilot_anti_virus_alarm_deleting_the_exe_files/) _2026-08-28 · /u/Imaginary-Island799_ Synthpilot website looks pretty professional. At least I had no fear to try to install synthpilot, but our Antivirus software flagged some packed/Python antivirus payload and deleted the files from hard disc. I wonder where did the infection come? Did the developer infect it deliberatly? Or is it a false alarm and there is no virus? At least on our PC install is not possible. Any comments,… ## [I Want to sell Artix7 100T fpga development board](https://www.reddit.com/r/FPGA/comments/1w0nqze/i_want_to_sell_artix7_100t_fpga_development_board/) _2026-08-28 · /u/GeForceYT_ Xilinx XC7A35T / XC7A100T Artix 7 FPGA IC 256Mb SDRAM 8MB SPI FLASH Memory On-Board USB JTAG Programmer USB to UART Interface 4 Digit Seven Segment Display WiFi 802.11 b/g/n Bluetooth 4.0 BLE 12 bit VGA Interface HDMI Out 50 MHz Clock ADC 4 channel Temperature Sensor LDR Interface SPI DAC 2x16 LCD Display Micro SD 16 Slide switches 5 Push Button 5v Buzzer 16 LEDs 31 External I/O's. Is this enough… ## [Built and validated a custom AXI4-Lite peripheral on Zynq UltraScale+](https://www.reddit.com/r/FPGA/comments/1w0mgzm/built_and_validated_a_custom_axi4lite_peripheral/) _2026-08-28 · /u/Frank-Issuer50_ Cortex-A53 ↔ FPGA fabric on real hardware I’ve been working on a ZCU104-based control architecture where the Cortex-A53 in the Processing System communicates directly with a custom SystemVerilog peripheral implemented in the Programmable Logic through AXI4-Lite. The PL peripheral exposes a memory-mapped register bank for control, thresholds, PWM configuration, status, sensor values and version… ## [DO-254 effort ratio](https://www.reddit.com/r/FPGA/comments/1w0l67d/do254_effort_ratio/) _2026-08-28 · /u/LastTopQuark_ For those who have done DO-254 DAL-A, how much additional effort did it add, versus the same design completed as if it were commercial? submitted by /u/LastTopQuark \[link\] \[comments\] ## [Lattice MIPI IP RX Implementation](https://www.reddit.com/r/FPGA/comments/1w0kf2x/lattice_mipi_ip_rx_implementation/) _2026-08-28 · /u/Ornery\_Arm\_6800_ Hello I have started working with Lattice and the CrossLInk-NX family to implement an MIPI RX interface. I have looked at their MIPI CSI/DSI IP, to get started quickly, but I still feel there are some uncertainties when setting up the IP....like the different clocks that are used but I dont really understand how they are used? As a start I have setup the IP in RX mode, so I will receive data that… ## [FPGA Horizons London - Expanded places for AMD Vivado AI Lab](https://www.reddit.com/r/FPGA/comments/1w0jz6z/fpga_horizons_london_expanded_places_for_amd/) _2026-08-28 · /u/adamt99_ submitted by /u/adamt99 \[link\] \[comments\] ## [Open directory of blogs (Sponsored)](https://crawlproof.com/a/DBblNp0QmrFt) _2026-08-28 · **Sponsored**_ Drop URLs or OPML — get per-blog pages plus machine-readable JSON, OPML, text ## [Interview prep](https://www.reddit.com/r/FPGA/comments/1w0jx7s/interview_prep/) _2026-08-28 · /u/spenchhhh_ Hi! I'm currently pursuing my BS in computer engineering with a focus on hardware, and since I'm going to be at an internship in the fall, I was wondering if anyone wanted to study for interviews or just yap in general about FPGAs or anything. Send me a dm if you're interested! Always happy to learn more about anything submitted by /u/spenchhhh \[link\] \[comments\]