Recent content on Pranav's Internet Home
A 17 Year Old Kid 
 When I first walked into college, engineering wasn't a dream of mine. I had chosen Electronics and Communication Engineering because I had some time tinkering with electronics before thanks to my uncle,
but beyond that I had very little idea what engineering actually meant. I wasn't someone with a grand roadmap, a list of goals, or a vision of where I wanted to be in…
UPMEM - Bringing Processing-in-Memory Out of the Lab 
 Engineers love seeing their ideas and designs come to life. By now, we have seen multiple architectures like Tesseract and PEI but one question any of us genuinely would have
is whether: Hmm... cool, but has anyone actually built one? 
 
 [!Surprise]
Yep, very much so! 
 
 UPMEM is the first commercially available…
PEI - Making Near Memory Computing Feel Like a Normal CPU Instruction 
 So Tesseract made one thing obvious: 
 
 Rewriting an entire application to execute near memory isn't exactly easy. 
 
 That is precisely the problem PIM-Enabled Instructions (PEI) tries to solve. Instead of offloading the entire application,
PEI says: 
 
 Hmm, what if we could just offload a…
Tesseract - When the Processor Moves Next Door to Memory 
 After spending the last few days exploring Processing-Using-Memory techniques like RowClone , Ambit , SIMDRAM and
 Processing-Using-SRAM , it's obvious that they all share the same philosophy: 
 
 Yeah, make the memory itself perform computation. 
 
 But upon changing lanes, we come across Tesseract where the…
Processing-Using-SRAM - When the Cache Becomes the Processor 
 We have seen enough magic happen in DRAM via RowClone , Ambit and SIMDRAM . As I progressed in the later chapters of
the primer I came across Processing-Using-SRAM, which asks a different question: 
 
 If DRAM can compute, why not experiment with caches? 
 
 Modern CPUs contain tens of megabytes of SRAM spread…
SIMDRAM - Turning DRAM Into a Programmable SIMD Engine 
 After reading RowClone and Ambit , as we progress in the Processing-Using-Memory saga I wanna introduce you guys to a framework called SIMDRAM . 
 If we recall from Ambit, it demonstrated that DRAM can perform logic operations using two primitive operations: Majority(MAJ) and NOT. Since MAJ and NOT form a functionally complete set,…
Ambit - When DRAM Accidentally Becomes a Logic Gate 
 As I read further into Onur Mutlu's Primer on Processing-in-Memory , I came across another fascinating Processing-Using-DRAM (PUM) mechanism called Ambit 
(stands for A ccelerator-in- M emory for bulk Bit wise operations). 
 Many modern applications perform large numbers of bitwise operations on massive datasets. These include…
RowClone - Copying Data Entirely Inside DRAM 
 I have recently been reading about Onur Mutlu's Primer on Processing-in-Memory and one of the most fascinating Processing-Using-DRAM (PUM) ideas I came across recently is RowClone . 
 Modern systems perform a memory copy by moving data from DRAM, across the memory bus, through the CPU/cache hierarchy, and then back to the DRAM. Even though…
The False Confidence 
 Blog 1 ended with what felt like a satisfying explanation. DRAM is slow, the cache hierarchy exists to hide that fact, and if your working set grows large enough to spill out of cache, you start paying the full cost of main memory access. I even had the experiments to back it up: the 64-byte cache line showed up right where the hardware said it would, and the latency…
Understanding Isn't the Same as Execution 
 A few weeks ago, after my HPC / Computer Architecture exam, I had a bit of an existential crisis. 
 Not the "I don't understand this field" kind but more like: 
 
 I can understand fairly complex systems, so why do I still make frustratingly silly mistakes sometimes? 
 
 The exam had actually gone well overall, but I messed up…
My laptop's CPU can do billions of operations per second. I know this because
the spec sheet told me, and I believed it, because I am a trusting person. 
 So when I wrote a program to scan a 1GB array and it took 400 milliseconds,
I was confused. That's not billions of anything. That's just... slow.
Embarrassingly slow. The kind of slow that makes you question your life choices.…
Why I Built Herald 
 Microcontrollers are great, until you ask them to do math. 
 Try throwing trigonometry or signal processing at a small MCU and things slow down very quickly. This is especially true for cheaper or simpler chips that either do not have a floating point unit or rely on relatively expensive hardware support. Even when FPUs are available, they are not always the best…
So you're sold on RISC-V. You've seen the vision. Now comes the question every beginner asks: "Okay, but how do I actually start?" 
 In the previous post , we explored why RISC-V is the "Linux of hardware" and how it's making processor design accessible to everyone. Now let's talk about the actual tools that let you build, simulate, and hack on real processors. 
 The good news? You don't…
Introduction 
 In this blog, I share a small but meaningful design I submitted to the TinyQV tapeout program , what it is, why it matters to me, and what I learned along the way. Before we understand what my design is all about, let’s be clear with some common terminologies I use in this blog. 
 
 What is TinyQV? 
 Tiny-QV is a collaborative competition under the Tiny Tapeout…
The Hidden Half of Computing 
 Most of us discover FOSS through software: cool Linux distros, editors, frameworks and many other tools that make our life easier. But beneath all that is a world not many of us think about: the microchips that run our code. All this while, this world was locked away behind billion-dollar corporations and closed Instruction Set Architectures . 
 Say hello to…
Introduction 
 You’ve probably heard the term “System-on-Chip” before. Maybe it popped out from our daily usage of Smartphones, Automotive Vehicles or even a Raspberry Pi board! It sounds important (it is important), maybe even futuristic. But let’s rewind for a moment and ask the real question: 
 What is a System-on-Chip, really? 
 I’ve wanted to understand this for a long time. But…
Introduction 
 Aetheron is a small but complete RISC-V System-on-Chip , built entirely in Bluespec SystemVerilog and run in simulation. It features a pipelined CPU, memory-mapped peripherals, my own minimal TileLink interconnect, and can boot minimal bare metal C programs — all stitched together from scratch. 
 But it’s more than just a collection of modules. 
 I’ve always loved the…
A tiny DSP designed for constrained microcontrollers. 


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 Hi, I'm Pranav 👋 
 
 I'm an undergraduate electronics student interested in computer
 architecture, memory systems, and digital hardware design.
 
 
 My current interests include DDR memory controllers,
 processing-in-memory architectures, and understanding how modern
 systems move, store, and process data.
 
 
 Most of my work lives on GitHub ,…
About Me 
 
 
 
 
 My first technical talk at HSP's FOSS Talks 3.0 ! 
 
 Hi, I'm Pranav. 
 I'm an undergraduate electronics student interested in computer architecture, memory systems, and digital hardware design. I enjoy understanding how modern systems move, store, and process data, and spend much of my time exploring memory architectures and their performance…

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