Distortion effect for synths

• 5 June 2025

I have designed and built a distortion effect with input and output impedances as well as expected signal levels working well with synthesizers. It is very simple and minimalistic, but then again it doesn’t take much to distort a signal. Most of the design was done plugging simple models into SymPy and then using ngspice to verify the results. Assembled at home with an oven and some bad hand soldering.

The distortion effect is built from four (well, six) parts:

• input buffer – provides well controlled high input impedance to the external input, low output impedance to the following stage
• gain stage – where the actual distortion is happening
• diode clipping – more distortion and compression of the signal
• output stage – volume control and output buffer with low output impedance

There is a second copy of both gain stage and diode clipping that can be enabled with a switch to provide even more gain and distortion.

All parts of the effect are built using quite standard MMBT2222AL npn transistor. Power supply is 12V which is also relatively common value and provides enough headroom for expected signal levels.

Input buffer

The main part of the input buffer is an emitter follower with its biasing network. To design it I use the following set of equations describing the behaviour of the transistor in the forward-active mode:

That’s transistor current gain, base-emitter turn-on voltage (i.e. the forward voltage of the base-emitter diode), and the Ohm’s law for the emitter resistor. Biasing network is a voltage divider described by the Ohm’s law and Kirchhoff’s current law:

All of those are quite simple and I use SymPy to work with them. The main inputs are power supply voltage and transistor characteristics and . Then I can either “design” or “simulate” the circuit depending on which values I provide: providing the desired operating point gives me the resistor values, while if the resistors values are provided I get the operating point.

To find out the operating point I need to know: , , and . In emitter follower base voltage is set at midpoint to maximise available voltage swing. Current through the bias network is chosen to be relatively large in comparison to the base-emitter current (to reduce dependency on exact value). That leaves collector-emitter bias which, among other things influences the input and output impedance of the emitter follower. I chose 1.5mA.

With those value SymPy can solve the set of equations and return the resistor values. The next step is to find the closest values from the series of preferred numbers. I use 1% resistors, but decided to restrict search to E12 values as getting the exact values is not that important and doing this gives me quite effective BOM minimisation.

After rounding resistances to the closest E12 values. I now plug those into the equations describing the circuit to get back actual operating point and check that it is still close enough to the desired one.

There are some additional components in the input buffer apart from the emitter follower. The main purpose of R1 is to limit current and avoid excess noise while plugging in cable while the effect is on. R2 is there to ensure that DC operating point is well defined. C2 and C3 block the DC voltage. They need to be large enough to avoid cutting too much of lower frequencies.

To model this part of the circuit I use ABCD-parameters. Each component is a two port network: series resistance R1, shunt resistance R2, series capacitance C2, and the emitter follower which is just replaced by its input impedance (shunt). ABCD-parameters make it easy to describe such cascaded networks and computing the behaviour of the whole circuit becomes matrix multiplication of individual stages.

First step is to set capacitance of C2 to infinity and compute output voltage taking into account only resistances. Then I get SymPy to solve those equations for get me capacitance at which the loss at 20Hz is, rather arbitrarily chosen, 0.1dB. In this particular circuit that gave me the capacitance of at least 1889.7nF. However, there are more DC blocks in different parts of the whole effect, and I ended up choosing 47µF for all of them. That value is too large for class 1 ceramic capacitors and class 2 is not suitable to use in the signal path (large capacitance loss due to DC voltage, microphony) so I used electrolytic capacitors.

The final step is to generate the netlist for ngspice mainly as a way of verifying that the simple models I am using is indeed describing the circuit well enough. DC simulation gives me voltages and currents, while AC simulation gives me gain, input and (after attaching appropriate current source to the output) output impedance.

Gain stage

The gain stage is a common emitter amplifier providing voltage gain and an emitter follower lowering output impedance (needed by the next stage). The emitter resistor of the common emitter is bypassed at AC with capacitor C7 and a potentiometer is used so that the gain can be controlled from 0dB to over +40dB. The emitter follower doesn’t need its own biasing network since the collector voltage of the common emitter provides sufficient biasing.

The design process of the common emitter is similar to the emitter follower described earlier. There is now a collector resistor which adds one more equation that is just Ohm’s law.

The operating point is set so that without bypassing emitter resistor the gain is 0dB. Furthermore, I want to use 10kΩ potentiometer which more or less determines the values of both emitter and collector resistors, since the gain of common emitter is . Collector voltage is at two thirds of the power supply voltage, while emitter voltage is as a third of the power supply voltage. That maximises available voltage swing for both input and output. With those constraints collector-emitter current ends up being 0.5mA.

I use a logarithmic potentiometer, which gives me a relatively good, close to linear change in dB gain. This was checked by fitting an exponential curve to the potentiometer response provided in the datasheet and then computing the gain of the common emitter amplifier.

It is also worth considering how this gain stage is going to distort the signal. Of course, at the sufficiently high gain the output signal will reach maximum or maximum possible value and get clamped. However, there’s also the case when large enough input signal will cause the base voltage to exceed collector voltage and the transistor will no longer be in the forward-active mode. This can happen even at low gain and will fold the output signal. This is good, this is a distortion effect.

Diode clipping

The next stage is clipping signal with diodes. Admittedly, this part involved most manually chosen values. An approximation of a diode behaviour is that it will start conducting only if the voltage on its terminals exceeds diode forward voltage. That forward voltage depends on the semiconductor type and its doping profile. For silicon diodes it tends to be around 0.7V which would clamp the signal a bit too much. I opted for green LEDs with a forward voltage of around 1.8V. There’s also a potentiometer that provides some control over the aggressiveness of diode clipping. It is again a 10k logarithmic potentiometer. The actual response depends on the output impedance of the previous stage, adjustment resistor R16 and the input impedance of the next stage. The following graph shows the input vs. output voltage with various potentiometer settings.

R24 provides well defined DC operating point. C11 cuts high frequencies a little and was chosen during early breadboard-based prototypes.

Output stage

The final stage is an attenuator providing volume control, low-gain common emitter amplified and emitter follower driving the external load. The design of this stage was very similar to the gain stage, though the emitter resistor is not bypassed and the gain of the common emitter is fixed at around ~4x.

The collector current of common emitter is set at 1mA, while the emitter follower is set at 5mA to make sure that output impedance is low enough and it is able to drive difficult loads. This is particularly relevant as in the emitter follower configuration the BJT can only source current which can cause asymmetric clipping if the value of the emitter resistor is not low enough compared to the load.

I used ngspice to plot total harmonic distortion of the output stage.

The point at which it starts distorting is clearly seen, but even before that the THD is not great. Then again, this is not exactly the value is was trying to minimise in this circuit.

Similar to their counterparts in the input stage, R22 is providing well-defined DC operating point, R23 is limiting current.

PCB layout

There are two DPDT toggle switches. One provides true bypass for the whole circuit. The other enables a second copy of the gain and diode clipping stages (inserted just before the output stage). I use dual potentiometers for both gain and diode clipping so that both stage are controlled together. It is a 4 layer PCB which is my default that I use for most designs, with dedicated ground and power planes on internal layers. Since the whole effect provides over +80dB of gain it would be bad if there was significant coupling from the output of the second stage to the input of the first stage. I played it safe and made sure that all traces carrying signals of different magnitudes are separated by ground. Otherwise, the board is rather simple, it size and location of potentiometers and switches is determined by the user experience and my idea of the enclosure design. All other components fit easily around that. I assembled the board myself so to make my life easier I used 0603 packages for all resistors, diodes, and ceramic capacitors.

Output buffer (5mA collector current) and input buffer (2mA collector current) are quite noticeable on the thermal image. Otherwise, no surprises there.

One thing I didn’t mentioned much so far is the power supply. All parts of the circuit use 12V straight from the power input. This was deliberate decision as even a linear regulator would be by far the most complicated component on the board (which felt a bit silly) and it is quite fine when good quality lab power supply is used. It is considerably less fine when wall warts of unknown brand are powering the effect as demonstrated on the following graph (max gain, both stages enabled).

Lab power supply should be relatively easy to identify in this graph. In practice this is not a big problem, but if I decide to do another revision, I will probably reconsider adding a linear regulator with good power supply rejection ratio.

Full schematic is available here. Proper enclosure is still work in progress.