Arm’s Cortex A725 ft. Dell’s Pro Max with GB10
Arm’s 7-series cores started out as the company’s highest performance offerings. After Arm introduced the performance oriented X-series, 7-series cores
Chips and Cheese
The Devil is in the Details
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CES 2026: Taking the Lids off AMD’s Venice and MI400 SoCs
Hello you fine Internet folks, Here at CES 2026, AMD showed off their upcoming Venice series of server CPUs and
Diving into Qualcomm’s Upcoming Adreno X2 GPU with Eric Demers
Hello you fine Internet folks, Today we are talking about Qualcomm s upcoming X2 GPU architecture with Eric Demers, Qualcomm s GPU
Inside Nvidia GB10’s Memory Subsystem, from the CPU Side
GB10 is a collaboration between Nvidia and Mediatek that brings Nvidia’s Blackwell architecture into an integrated GPU. GB10’s GPU has
SC25: The Present and Future of HPC Networking with Cornelis Networks CEO Lisa Spelman
Hello you fine Internet folks, Today we have an interview with the CEO of Cornelis Networks, Lisa Spelman, where we
Nvidia’s B200: Keeping the CUDA Juggernaut Rolling ft. Verda (formerly DataCrunch)
Nvidia has dominated the GPU compute scene ever since it became mainstream. The company’s Blackwell B200 GPU is the next
SC25: Estimating AMD’s Upcoming MI430X’s FP64 and the Discovery Supercomputer
Hello, you fine Internet folks, At Supercomputing 2025, EuroHPC, AMD, and Eviden announced that the second Exascale system in Europe
Evaluating Uniform Memory Access Mode on AMD’s Turin ft. Verda (formerly DataCrunch.io)
NUMA, or Non-Uniform Memory Access, lets hardware expose affinity between cores and memory controllers to software. NUMA nodes traditionally aligned
SC25: HACCing over 500 Petaflops on Frontier
Hello you fine Internet folks, Here at Supercomputing the Gordon Bell Prize is announced every year. The Gordon Bell Prize
Qualcomm’s Snapdragon X2 Elite
Hello you fine Internet folks, Last week I was in San Diego at Qualcomm’s Headquarters where Qualcomm disclosed more information
Strix Halo’s Memory Subsystem: Tackling iGPU Challenges
Editor’s Note (11/2/2025): Due to an error in moving the article over from Google Docs to Substack, the “Balancing CPU
Evaluating the Infinity Cache in AMD Strix Halo
Strix Halo is the codename for AMD’s highest end mobile chip, which is used in the Ryzen AI MAX series.
AMD’s Chiplet APU: An Overview of Strix Halo
Hello you fine Internet folks! Today we are looking at AMD’s largest client APU to date, Strix Halo. This is
Panther Lake’s Reveal at ITT 2025
Hello you fine Internet folks, At this year’s ITT, Intel announced their upcoming client SoC, Panther Lake (PTL) along with
Interviewing Intel’s Chief Architect of x86 Cores at Intel Tech Tour 2025
Hello you fine Internet folks, I was at Intel Tech Tour this year where Intel talked about their upcoming Panther
AMD’s EPYC 9355P: Inside a 32 Core Zen 5 Server Chip
High core count chips are headline grabbers. But maxing out the metaphorical core count slider isn’t the only way to
A Look into Intel Xeon 6’s Memory Subsystem
Intel’s server dominance has been shaken by high core count competition from the likes of AMD and Arm. Xeon 6,
AMD’s Inaugural Tech Day ft. ROCm 7, Modular, and AMD Lab Tour
Hello you fine Internet folks, I was invited to AMD s Austin Headquarters where AMD held their inaugural Tech Day where
Everactive’s Self-Powered SoC at Hot Chips 2025
Hot Chips 2025 was filled with presentations on high power devices. AI can demand hundreds of watts per chip, requiring
AMD’s RDNA4 GPU Architecture at Hot Chips 2025
RDNA4 is AMD’s latest graphics-focused architecture, and fills out their RX 9000 line of discrete GPUs. AMD noted that creating
Intel’s E2200 “Mount Morgan” IPU at Hot Chips 2025
Intel’s IPUs, or Infrastructure Processing Units, evolved as network adapters developed increasingly sophisticated offload capabilities. IPUs take things a step