Retro gaming and computing experiments by nand2mario
I released z386 , an open-source 80386 CPU core, in May and added the 80386 early-start optimization in June. Early start overlaps address generation for one instruction with completion of its predecessor. It was an important 386 performance feature, but it also previewed the more systematic i486 pipeline. The MiSTer core needed more performance, so I continued in that direction and added further…
When Intel designed the 80386, they gave it a trick for hiding memory latency: Early Start . Instead of waiting for an instruction to reach its memory micro-op, the 386 begins the next instruction's address work — effective address, segment relocation, the bus cycle — in the last cycle of the current instruction. Intel put it at about 9% of overall performance. It is also the source of the…
This is the fifth installment of the 80386 series . The FPGA CPU is now far enough along to run real software, and this post is about how it works. z386 is a 386-class CPU built around the original Intel microcode, in the same spirit as z8086 . The core is not an instruction-by-instruction emulator in RTL. The goal is to recreate enough of the original machine that the recovered 386 control ROM…
The FPGA 386 core I've been building now boots DOS, runs applications like Norton Commander, and plays games like Doom. On DE10-Nano it currently runs at 75 MHz. With the core now far enough along to run real software, this seems like a good point to step back and look at one of the 80386's performance-critical subsystems: its memory pipeline. 32-bit Protected Mode was the defining…
I'm building an 80386-compatible core in SystemVerilog and blogging the process. In the previous post , we looked at how the 386 reuses one barrel shifter for all shift and rotate instructions. This time we move from real mode to protected and talk about protection . The 80286 introduced "Protected Mode" in 1982. It was not popular. The mode was difficult to use, lacked paging, and offered no…
I’m currently building an 80386-compatible core in SystemVerilog, driven by the original Intel microcode extracted from real 386 silicon. Real mode is now operational in simulation, with more than 10,000 single-instruction test cases passing successfully, and work on protected-mode features is in progress. In the course of this work, corners of the 386 microcode and silicon have been examined in…
When Intel released the 80386 in October 1985, it marked a watershed moment for personal computing. The 386 was the first 32-bit x86 processor, increasing the register width from 16 to 32 bits and vastly expanding the address space compared to its predecessors. This wasn't just an incremental upgrade—it was the foundation that would carry the PC architecture for decades to come.
Happy New Year! The site has a fresh new design. I’ve replaced Hugo with a minimal, custom static site generator that suits my needs much better.
After 486Tang , I wanted to go back to where x86 started. The result is z8086 : a 8086/8088 core that runs the original Intel microcode . Instead of hand‑coding hundreds of instructions, the core loads the recovered 512x21 ROM and recreates the micro‑architecture the ROM expects. z8086 is compact and FPGA‑friendly: it runs on a single clock domain, avoids vendor-specific primitives, and offers a…
Since releasing 486Tang , I’ve been working on recreating the 8086 with a design that stays as faithful as possible to the original chip. That exploration naturally led me deep into the original 8086 microcode — extracted and disassembled by Andrew Jenner in 2020. Like all microcoded CPUs, the 8086 hides a lot of subtle behavior below the assembly layer. While studying it I kept extensive notes,…
Yesterday I released 486Tang v0.1 on GitHub. It’s a port of the ao486 MiSTer PC core to the Sipeed Tang Console 138K FPGA. I’ve been trying to get an x86 core running on the Tang for a while. As far as I know, this is the first time ao486 has been ported to a non-Altera FPGA. Here’s a short write‑up of the project.
A year ago, I added a softcore CPU to SNESTang , to make FPGA gaming cores easier to use. Over the past months, this allowed me to implement features like an improved menu system and core switching. While the softcore served its purpose, its limitations—slow performance, inability to handle complex peripherals like USB, and FPGA resource consumption—became apparent. Now is again the time to…
I've recently found myself frequently using the "ChatGPT to PDF" Chrome extension to convert ChatGPT conversations into PDF documents. The Deep Research discussions in particular contain valuable info worth preserving in ebook format. However they lack proper title pages. So here's a quick Python script to add a simple title page to PDF documents.
Universal Asynchronous Receiver-Transmitter (UART) modules are basic components in embedded systems, enabling serial communication between devices. While there are many free implementations available online, a new challenge arose during my work on the independent software stack for the Tang Console : non-integer clock multiples . This issue surfaced when FPGA cores running on clocks of different…
Today we discuss Sega Genesis (or Mega Drive). The 16-bit game consoles held a special place in game history. After the 8-bit machines became extremely popular in the mid-1980s, companies had more resources to pour into R&D of the next generation, leading to more sophisticated designs. And the users truly desired "arcade-level performance", hence the "Blast Processing" marketing by Sega. These…
GBATang has been improving pretty quickly since its release and just reached version 0.4 . More games are running. Graphics rendering has improved a lot. And sound bugs were fixed. Continuing part one , let us discuss the components that were not covered in the first post.
Here are a few tips and tricks for using the Gowin EDA IDE and Tang FPGA boards , such as Tang Nano 20K, Tang Primer 25K and Tang Mega 138K. These are small things that I wish I knew when picking up the Tang boards. Gowin is a relatively small FPGA vendor and documentation is not that complete. So I hope this is helpful for the community. If you are coming from Xilinx or Intel FPGAs, you may also…
Version 0.1 of GBATang is just released. It is the first FPGA core for a 32-bit console available for Tang FPGA boards (Tang Mega 138K and the upcoming 60K). The journey is an interesting one for me. This first blog post discusses the experience of porting and building this core, its overall technical design and in more details, the CPU part.
In part 1 , we discussed why we need a softcore for SNESTang, and how it can use SDRAM in a way that does not disrupt the gaming core. Now we need to provide a firmware program to to make the softcore useful, like displaying a menu. In this part, let's explore the building and loading of the RISC-V firmware to get the soft core to do useful work.
In the recently released SNESTang 0.3 , a softcore-based I/O system is added to enhance the menu system and file system support. Let us explore how this works. Part one of the article discusses why the soft core is necessary, choice of CPU to use and how it works with the SDRAM.