Build, Test, and Debug cGit - the hyperfast web frontend for Git, on Ubuntu Linux 24.04
A brief summary of getting started with cgit on Ubuntu Linux along with debugging a segfault we encountered
Private Island Networks
FPGA-based Networking and Machine Learning, Quick Turn Hardware Design and Manufacturing
Latest posts
Generating a PLL IP fails on Quartus Prime Pro
Generating a simple PLL IP for an Agilex 3 using Quartus Pro fails. See error below: Error: add_fileset_file: No such file C:/altera_pro/26.1/ip/altera/altera_iopll/top/{C:/Users/ /AppData/Local/Temp/alt0666_1092945879227822690.dir/0003_iopll_0_gen/
Volitio™ board
Will there be more information on your Volitio™ board, on: how many layers it has, the routing requirements? The handling of the required power on sequencing. Interfacing a gigabit ethernet transceiver using SGMII for 1000Base-T, code example possibly
Hardware Specification for Open Source Betsy Maker Board for FPGA-based Networking
Preliminary specification and reference manual for Altera Cyclone 10 LP based Betsy maker board for open source networking.
How do I import one PCB into another one with Kicad?
How can I import one PCB file into another one so I can reuse a snippet?
Machine Learning Module Powered by Altera Agilex 3
A summary of the design goals, issues, and work items in designing and manufacturing an Agliex 3 based daughter board for the Betsy maker board
Adding GPIO Bit Banging to an FPGA Open Source Project for Networking
Description of the steps taken to add GPIO bit banging for the Betsy maker board and Private Island open source project
Add a Packet Generator to FPGA Open Source Project for Networking
A summary of the steps taken to add a programmable packet generator for the Betsy maker board and Private Island open source project
Simulating Private Island and Betsy
Review the setting up a simulation of the Private Island open source project for the Betsy maker board and running an Ethernet simulation in Questa