6次魔方陣の総数 (回転、反転を除く) 17 753 889 197 660 635 632 数え上げ方法の解説YouTubeビデオ より入門的な解説「6次魔方陣を数え上げた話」 この値は数え上げを2回行って確認されています。 数え上げはクラウドサービスが提供する多数のGPUを利用して行われました。 使用された GPUの数やモデルは一定ではありませんが、 最初の数え上げには GeForce RTX-4090 で 80,000時間相当の延べ時間を要し、 2回目の数え上げには、性能改善されたプログラムを使って延べ 54,000時間を要しました。…
Move to the Japanese page The number of magic squares of order six counted up to rotations and reflections 17 753 889 197 660 635 632 YouTube video explaining the method to achieve the enumeration. manuscript presentation slides This number has been confirmed by completing the enumeration twice using hundreds of GPUs provided at cloud resource rental services. Though the number and models of GPUs…
Move to the Japanese page The number of magic squares of order six counted up to rotations and reflections 17 753 889 197 660 635 632 YouTube video explaining the method to achieve the enumeration. manuscript presentation slides This number has been confirmed by completing the enumeration twice using hundreds of GPUs provided at cloud resource rental services. Though the number and models of GPUs…
Strategies in counting magic squares For the definitions of terms, see this. Preparing 2N+2 magic series To construct a magic square of order N, We need 2N+2 magic series for rows, columns and diagonals which satisfy the following constraints: * Row magic series don t have common elements with each other.
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20240504.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20240504.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 1330 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
小集合の定義 魔方陣全体の集合を小集合に分けるために、いくつかの用語を定義します。 魔方組とその2進数表現 * n次の魔方組 とは、[1..n2]の範囲のn個の異なる整数からなる集合で、要素の和が
Definition of subsets We introduce some terminologies here to divide the whole set of magic squares into small subsets. A magic series and its binary representation * A magic series of order n is a set of n distinct integers in the range [1..n2]
魔方陣数え上げの戦略 用語の定義については こちらをご覧ください。 2N+2個の魔方組を用意する N次の魔方陣を作るには、以下の制約を満たす合計2N+2個の魔方組(行N個、列N個、対角2個)を用意する必要があります。
__device__ int cnext( const u64* __restrict__ vp, const int & nv, const int must_bit ) { int j = 0; #pragma unroll 1 for( int i = 0; i > must_bit; } j += __popc( __ballot_sync( AllLanes, p ) ); if( j != i + WS ) break; } return j; } __device__ int gather_cross( const u64* __restrict__ const & vp, const int & nv, const u64 & x…
Note added on 2024.06.20 Self complementarity related codes should be removed from functions MakeCols() and MakeColsLast() in order to optimize the performance for N=6. Complements of any rows never appear as columns in even order magic squares. /* See https://magicsquare6.net/ . Updated on 2023/09/18. Authored by Hidetoshi Mino hidetoshimino@gmail.com . */ #include #include #include #include…
Subtotals of semi-magic squares representative magic series in hex count md5 e00000007 481881029565160 55011afb3a92321a802326d6ed35671a d0000000b 467738336770141 7a8e6a1632c907d620a08f59ae53f5b2 c80000013 455544230201104 0bbd10407856a1e14d25065df0173e5a c8000000d 906479564244550 24c9405319789e678ef58354a70200e8 c40000023 444037026538696 9fda19a9f27a1095a80f7d98e84b9202 c40000015 883392280083774…
/* sms.cu Counting number of semi magic and magic squares up to permutation of rows and that of columns. To get the number up to rotations, reflections and M tranformations, multiply the result by N! x N! / 4. Compilation : nvcc -O3 -arch=sm_60 -maxrregcount=40 \ -Wno-deprecated-declarations sms.cu -lcrypto To omit md5 checksum, add a -DnoMD5 option. Then you may drop -Wnodeprecated-declarations…
Preliminary double-check done already Computing resources available in clouds are diverse in their performance, price and lifetime. To save cost, I had to continuously seek inexpensive resources and create instances in daily basis. The total number of instances ever created exceeded five hundreds. I conducted the following check as a minimal verification of the resouces:
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20240410.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20240410.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
Subtotal for each subset These numbers are counted up to M-transformations and should be multiplied by 24 to get the final results. Note: 3 of the following entries are known to be incorrect. They are kept uncorrected intentionally. representative magic series in hex count md5 e00000007 408638865451068 78e78031cb1e6b998036e1db4a64d246 d0000000b 409581501621759 618f28f440b6eb4c118760a1e56cf01b…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231201.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231201.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231129.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231129.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231121.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231121.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231120.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231120.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231117.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231117.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 Total warps: 6144 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644,…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231101.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231101.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231029.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231029.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20231012.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20231012.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20230929.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20230929.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20230926.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20230926.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20230926.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20230926.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
/* See https://magicsquare6.net/ . Updated on 2023/09/05. Authored by Hidetoshi Mino hidetoshimino@gmail.com . */ #include #include #include #include #ifndef noMD5 #include #endif #define MAX( x, y ) ( (x) > (y) ? (x) : (y) ) #ifndef N #define N 6 #endif #ifndef NTH #define NTH 1 #endif #define NN (N*N) #define AllBits ( ( 1ULL << NN ) - 1 ) typedef long long unsigned u64; inline int topbit( u64 v…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20230905.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20230905.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
An execution example on GeForce RTX-4090 $ nvcc -O3 -arch=sm_60 -maxrregcount=40 ms-20230131.cu -lcrypto $ time ./a.out 00000 e00000007 13745 180800250 ms-20230131.cu Size of long long unsigned : 8 topbit() works correctly. nvecs 32134 size of p_idx_c 2300 DevId: 0 #SM:128, #Blocks:2048 NVIDIA GeForce RTX 4090 r1:e00000007 r2:180800250 nrows 3116 n3rd 711 row_set.size() 5956644 00000 e00000007…
/* See https://magicsquare6.net/ . Updated on 2023/01/31. Authored by Hidetoshi Mino hidetoshimino@gmail.com . */ #include #include #include #include #ifndef noMD5 #include #endif #define MAX( x, y ) ( (x) > (y) ? (x) : (y) ) #ifndef N #define N 6 #endif #ifndef NTH #define NTH 1 #endif #define NN (N*N) #define AllBits ( ( 1ULL << NN ) - 1 ) typedef long long unsigned u64; inline int topbit( u64 v…