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This article evaluates the proficiency of 11 contemporary Large Language Models (LLMs) in performing electronic circuit analysis. 
 Utilizing OpenCode , an open-source agentic framework, the LLMs are tasked with analyzing a clock generator’s resistor-capacitor (RC) network defined in a KiCad 9.0 schematic. To facilitate LLMs’ comprehension, an efficient preprocessing methodology is…
Some days ago I ordered a testing PCB from PCBWAY , and today the package has arrived! 
 
 
 FRONT : 
 
 BACK : 
 
 As discussed in the previous article, this is a test-board for the future PCIe card with Agilex 3 FPGA. But presently - no FPGA. The board combines several power supplies (dc/dc converters), clock generator with level shifters, reset, and USB-JTAG: 

In hardware design, tedious manual data entry is a common bottleneck. I recently explored how the ‘AI revolution’ - specifically LLMs and GitHub Copilot - could automate a specific, repetitive task: importing BGA pad-to-die lengths into KiCad 9. The input Excel table, downloaded from Altera site, has around 270 rows, so the motivation to not do the import by manually entering numbers…
AGILA will be a new open-source board with the Altera Agilex 3 FPGA , 2 GB to 8 GB 
of LPDDR4 RAM and the PCI-Express interface . The Agilex 3 FPGA includes hard-IP support for PCI- Express interface up to Gen3 x4 and the LPDDR4 x32 up to 1066MHz (2133MT/s). The board form factor will be a low-profile PCI-Express card with the x4 edge connector. The upper edge of the board will be occupied by…
The picture below is an extract from Power-Supply Block Diagram of the official Agilex 3 Devkit. The FPGA requires multiple power supply levels: from 0.75V to 3.3V. Specification is found in altera document Power Management User Guide: Agilex™ 3 FPGAs and SoCs and details for particular device in Agilex™ 3 FPGAs and SoCs Device Data Sheet . 
 
 Minimum Set of Power Levels 
 This is the…
Theoretically, Agilex 3 FPGA does not require any external clock signals to load bitstream and to operate an (asynchronous) user design. However, in practice, all designs will need to supply some clock signals for use in EMIF (e.g. LPDDR4) or GTS (e.g. PCIe) and other integrated IP. To be specific in this post, we focus on clocking scheme of the Agilex 3 Devkit board (block diagram pictured…

 
 
 **What the local company manager expects: ** 1. Make all developers use gen-AI tools for coding 2. Expect productivity increase 3. Profit!! 
 What the AI-tooling company plans: 1. Make all developers use gen-AI tools for coding 2. When most are dependent, decrease the quality and increase the price 3. Profit!! 
 
 
 
 
 **What a developer should do: ** 1.…
Agilex 3 FPGA supports loading of the configuration bitstream by multiple methods. A method is selected by 3 strapping pins MSEL[2:0] (these are multi-purpose strapping pins). The common methods are: 
 
 
 MSEL[2:0]=111 => wait for JTAG download, 
 
 
 MSEL[2:0]=011 => normal QSPI Flash download mode 
 
 
 MSEL[2:0]=001 => “fast” QSPI Flash download…
Agilex 3 FPGA supports PCI-Express via its four GTS transceiver links . Each GTS physical link (tx+rx) supports up to 12.5Gbps transfer speed. On top of the GTS transceivers the FPGA implements hardened IPs for PCI-Express 3.0 x1-x2-x4, Ethernet 10 Gbe link, and USB 3.0 (only with HPS). 
 Available PCI-Express Throughput 
 PCI-Express speed is specified in generations: from 1.0 to 8.0…
Presently (2025) there are two perspective busses for connecting DRAM devices in embedded systems: 
 
 
 DDR3L 
 
 
 LPDDR4 (and its lower-power variant LPDDR4X) 
 
 
 The DDR3L supports traditional DDR multidrop bus topology with VTT termination and multiple memory devices sharing the address/control bus. The LPDDR4 is a completely different protocol and allows…
Ever since I attended the Altera FPGA workshMicronop featuring their new Agilex 3 device, I am thinking if Agilex could be the right FPGA to implement a general-purpose computation accelerator (i.e. a GPU) with a fast PCI-Express interface and a significant amount of DDR DRAM memory. 
 The following features of Agilex 3 FPGAs are notable in the context: 
 
 
 100k to 135k logic…
Recently I attended Arrow’s Agilex 3 FPGA workshop, which promoted, obviously, the new Altera Agilex 3 FPGAs. In the workshop we completed lab tasks using also the new AXC3000 Starter Kit that features the Agilex 3 FPGA. At the end of the day there was a quiz and so I happened to win one the AXC3000 boards for myself. In this article I present my first-look analysis of the board. 

There is an ongoing Indiegogo campaign called “ X65GS 65816 Gaming Console ”, see screenshot below. 
 I - as the creator of the x65 project - do not support and do not endorse this campaign . 
 In the campaign page they reused my own ‘amateur’ photos of that one x65-sbc device, which is right now on my work-desk at home. IT MEANS: they do not have the capacity or…
I started a new debugger tool for my x65 project. Previously I created a dozen of single-purpose python scripts (running on a linux PC) that let me single-step the CPU, read CPU registers, dump memory and so on. The scripts use a common ‘backend’ modules to connect to the x65 hardware over the USB / FTDI interface, but otherwise each script acts on its own. 
 These python scripts…
I designed an enclosure box for the x65-SBC computer . For modelling I used Siemens Solid Edge 2024 CAD software, of which I have the Employee Edition. (I think it is just similar to the free Community Edition , but I did not verify.) 
 
 The enclosure box is composed of ’top’ and ‘bottom’ parts which can be 3d-printed individually. The parts are screwed together…
As mentioned in previous post , Matej asked me if Dreamtracker app is running on X65 . I told him that yes, it should run, but better to test it first myself. I downloaded Dreamtracker in its current version V0.71, fired it up, and well, after a promising start - I could see its main menu for a split second - the program crashed into the Monitor …. Well, that felt embarrasing :o 
 This…
It’s Autumn again and I am revisiting my Project X65 . My list of to-do tasks is endless and growing still :-) 
 
 
 finishing tests of the A1 prototype 
 
 
 load BOM to Mouser 
 
 
 testing the USB interface 
 
 
 better ESD concept 
 
 
 indication of stopped CPU 
 
 
 consider new extension connector 
 
…
In the previous post I have mentioned that I am working on a port of the 32-bit Forth interpreter OF816 to my X65-SBC , an 8/16-bit retro computer that I am building. The software runs on the X65-SBC in the 65C816 processor, but the user textual input and output was so far realized via the USB/UART interface terminated on a host PC in a terminal emulator (e.g. putty). 
 As the next logical…
I am working on a port of the 32-bit FORTH interpreter OF816 for my X65-SBC computer with the 65C816 CPU. The OF816 was created by mgcaret and is available on github. I made a fork of the OF816 project and added a new branch for my work: x65-sbc . 
 The OF816 already supports a couple of 65C816-based systems: GoSXB, Apple IIgs, Neon816 and the W65C816SXB. I added a new subdirectory X65 in the…
Symptoms: Running Fedora 38 and 39 with kernels 6.7.7 on AMD Ryzen 5 with AMD GPU RX570 (Sapphire Radeon PULSE ITX RX 570 4GD5, 4GB GDDR5) sometimes results in a blank screen (no video signal, monitor going to sleep mode) after the boot. The display manager (sddm, wayland) does not start (or is not visible, there is no video) and it is not possible to login or switch to a virtual console.
Modern microcontrollers and microprocessors have built-in facilities for external debuggers to read/write registers, set breakpoints and generally fully control the CPU. This is one of the main usecases of the standard JTAG interface. The 6502 and 65816 CPUs were created more than a decade before the first version of JTAG was even defined. They contain no support for external debuggers whatsoever.…
In the last 2 months I have re-done my X65 double-decker computer into a Single Board Computer (SBC). 
 
 The single-board version fixes some of the electrical problems I had on the first version and it has way better signal integrity thanks to the 4-layer PCB. Other than that, the feature-set is basically identical. 
 
 
 added the mono speaker with volume control. 
 
…
In X65 the assembled CPU is either the 8-bit W65C02S or 16-bit W65C816S. The W65C816S is (partially) compatible with W65C02S. This page summarizes the differences from the low-level hardware point of view and in the case that the 65C816 is running in the 8-bit Emulation Mode . 
 These two photos shows the processors assembled on X65 main board: 
 
 
 Processor Pinout Comparison…
This document discusses the FM sound synthesis in the Commander X16 and in my x65 computer . 
 Sound in Commander X16 
 Sound in Commander X16 is generated by two sources that are mixed together: 
 1) by the Programmable Sound Generator (PSG) in VERA FPGA, and 
 
 by the MIDI FM-synthesis chip YM2151. 
 
 The following picture is a block diagram of the sound subsystem…
SNES Controllers typically look like this: 
 
 SNES controller is a cheap and easy way how to add a joystick interface to a DIY project. One controller can be cheaply had from aliexpress or similar for around 2 USD. 
 The controller has just 12 digital (on/off) buttons organized in various patterns, as you see in the photo: D-pad, ABXY buttons, two shoulder buttons, start and select.…
X65 is a retro/modern 16-bit computer that I designed inspired by the architecture of Commander X16 (CX16). It is based on the legendary 6502 / 65816 processors, which, incredibly, are still in production in 2023 and beyond. 
 X65 is an open-source - you can find all schematic and sources in my GIT repository: 
 https://github.com/jsyk/x65 
 Mechanical design files (enclosures) are…
My Open-X65 project achieved a milestone: the unmodified X16 ROM can be loaded and runs! I manually typed in a BASIC maze program, which draws some ASCI graphics: 
 
 

The Open-X65 GIT repository is now public: 
 https://github.com/jsyk/x65 
 Note: this is not a release! The project is very much a work-in-progress. You have been warned ;-)
Since the first post a lot of happened: 
 
 
 Motherboard PCB (bottom) has arrived, it is now part-way assembled with components and working quite well. First test-SW (a few instructions in a loop) is running OK. 
 
 
 I designed the second PCB (top) with video (VERA), audio (AURA - FM synth) and ethernet port. This was also manufactured, part-way assembled and now I have…
I am starting a new hobby project called X65 : I intend to create an open-source computer based on the “vintage” 6502 processor , which is still in production as the W65C02. The original 6502 was used in many home personal computers of the ’80s: Commodore, Atari, Apple II and so on . My computer will be called OpenX65 . 
 Features as planned : 
 
 
 use W65C02 and…
Mywayback is a complete rewrite of my previous timeback archival tool. It is now available on the github: https://github.com/jsyk/mywayback 
 Main features: 
 
 Python 3.x in Windows (with NTFS-only) and Linux. Requires the package sortedcontainers . 
 Automatic deduplication of source files using SHA256 
 Hashes of the files are stored in a hash-cache under the target…
Engineers’ Tribute is an endless well of electronic technology sites, perfectly suited for studying during long winter evenings (or lockdowns.. :-) ) 
 Checkout this handy wire-gauge chart made by PEI-Genesis . The download link is right at their front page: 

Go see my Vacuum Tube watch “EVERGLOW” V2.1 

The Vacuum Tube Watch project is now released in version V2.1 “EVERGLOW”. Go see it via the “Projects” menu above. 
 
 Enjoy!
The “ EVERGLOW ” Watch is a vacuum tube clock put on the wrist: 
 
 
 Features: 
 
 Soviet VFD tube IVL2-7/5 
 Time (24h), Date, (dd-mm-yyyy), day of week (Mo-Tu-We-etc). 
 Alarm clock (7-day) with a beeper. 
 Stop-watch (00:00 => 9:59:59) 
 Count-down clock (99:59 => 00:00) 
 50mAh LiPo accumulator (lasts 1-2 weeks), charging over a Micro-USB…
UPDI - Unified Program and Debug Interface - is the new programming and debugging interface on new ATtiny MCUs from Microchip. The UPDI requires just a single pin on the MCU, so it is very suitable for low-pin count chips. Physically it is implemented as a bidirectional (half-duplex) UART protocol. UPDI pin is typically located with the RESET pin on the ATtiny MCUs. A programmable fuse in the MCU…
I created a smal 100x100mm PCB mini-panel of some of the SMT breakout boards from Adafruit . Each mini-panel contains: 
 
 3x SOIC-20 (A-side) and TSSOP-20 (B-side) 
 5x SOIC-16 (A-side) and TSSOP-16 (B-side) 
 5x SOIC-8 (A-side) and MSOP-8 (B-side) 
 4x SOIC-8 (A-side) and TSSOP-8 (B-side) 
 
 Note: All SOIC pads have 1.27mm pitch, all TSSOP pads have 0.635mm pitch.…
Here you can find documentation about my DIY Analog Curve Tracer . 
 
 
 
 Analog Curve Tracer 
 

A signature curve tracer is a simple yet useful device in any electronics lab. It shows in picture form the V/A characteristic of a two-terminal device under test (DUT), such as a resistor, a capacitor, a diode or any PN junction. It could also be used to characterise a transistor or an optocoupler, if additional drive circuit for the third terminal is used. Another use is in locating circuit…
New AVR processors from Microchip/Atmel use a 1-wire UPDI interface for flash programming. You could use either AVR ICE or Pickit 4 as the “official” programmers (I did not test any of them). Both of these cost >50 EUR. 
 A good alternative, presented in this post, is to modify the ATtiny817 Xplained Mini board (costs ~10 EUR) and use it as the UPDI programmer: 
 

NXP’s PN7120 is NFC controller for contactless communication at 13.56MHz. It interfaces with the host CPU via the I2C bus. The I2C slave address of PN7120 is 0b010100Lx, where L is a configurable LSB of the address (by pin B2, I2CADDR0), and x is the standard I2C R/W bit. Hence the normal I2C address is either 0x28 or 0x29: 
 // write to device at address 0x28,…
Once upon a time, I decided it is a good time to upgrade the version of gcc compiler we use in our ARM926-based firmware project. Historically, this project uses gcc version 4.6, which is quite outdated nowadays (January 2018). In a different project, built around ARM-Cortex, we already successfully use the gcc version 5.4.1 (Linaro release in January 2017), so I wanted to upgrade our ARM926…
The X86 has always supported unaligned accesses. In the ARM world the first architecture that supported unaligned accesses in hardware was ARMv6. The architecture was implemented in the ARM11 core around the year 2002 and onward. There is an excellent article at ARM Infocenter giving technical details: 
 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15414.html 
 The…
This is Part 2 of a two-part series on Ethernet RMII. In Part 1 I described my hardware setup and basic Ethernet operation. In the second and final part I will describe the design of specialized MAC cores I implemented on FPGA, and there will be measurements to see how much throughput and latency the system can achieve.
This is Part 1 of the two-part series on Ethernet RMII. Part 2 is also available. 
 Imagine your application requires a non-standard periphery controlled by an embedded processor. What options do you have? The periphery can be implemented in an FPGA; depending on periphery complexity you can choose an optimal FPGA that fits your budget. Where the processor goes? There are three possibilities:…
How to export PCB design from the free Altium Circuit Maker v1.0.4 so that it can be submitted to OSH Park fab. This took me an evening to figure out; OSH Park service was bitching about missing “outline” and/or drill files.

 https://www.youtube.com/watch?v=dQuFrbmcv-0

 [half-way through; click a pic to see hi-res] 
 [connections to bga] 
 [finished “product”] 
 And it (almost) worked! Though not at-speed, because of wire inductances.
During pre-Christmas sale on Seeed Studio Bazaar they offered these digital radio modules with the nRF24L01+ chip for only US$0.81 each. So I bought 10 of them outright :-) 
 
 What would YOU suggest to do with them? Build a wireless flower life-support monitoring network? A mobile voice communications radio system? Retrofit them into talking toasters and robotic vacuum cleaners? Let me…
This issue bugged me a long time, finally I solved it this evening. Debugging code on my PIP-Watch using my ST-LINK-v2 JTAG debugger was very painful because the debugger software – OpenOCD and GDB – kept failing randomly during debug sessions with a rather cryptic message: 
 Error: jtag status contains invalid mode value - communication failure
Polling target stm32f1x.cpu…