I recently held a presentation at the 10th MicroTCA Workshop for Industry and Research , where I presented some hardware we have developed, discussed the advantages of using SoCs, and showed a couple of examples where we successfully leveraged the features of these devices. At my day job the dataflow through …
A Primer on Memory Consistency and Cache Coherence, Second Edition Authors: Vijay Nagarajan, University of Edinburgh Daniel J. Sorin, Duke University Mark D. Hill, University of Wisconsin, Madison David A. Wood, University of Wisconsin, Madison "This primer is intended for readers who have encountered memory consistency and cache coherence informally …
My last blog post on this topic explored the PCI Express connections on this board. I have determined that the board contains a custom FPGA with two Hard IPs for PCIe, where the commercially-available part only contains one. At the end of the post I explored different options on how …
Xilinx Adapt 2021 Day 1 (2021-09-07) Adaptive Computing: Innovation Accelerated [Ivo Bolsens (Xilinx)] the hardware is adapted, rather the other way around DSA growing gap between the moore's law and AI requirements requirements: 6G (100 Gbps, 0.1 ms latency) Xilinx wants to be a platform company Vivado/FPGA -> Vitis …
A short intermezzo from all FPGA-related stuff, this time we deal with an 8051-based USB device. This blog post describes how I converted an ISDN modem (with a USB connection) to a USB-to-UART cable. During my vacation at my parents' house, I wanted to access the UART on the Ultra96 …
Here are my notes from the Chisel Community Conference China 2021. The conference took place on June 26th 2021, and was organized as a hybrid conference, open to both on-site and remote participants (over Zoom). The organizers have promised that the recorded talks will be made available online in the …
In this blog post I describe my tinkering with the interconnect architecture of the Xilinx Zynq MPSoC. I specifically focus on the Performance Monitoring Unit (PMU) integrated into the Cache Coherence Interconnect (CCI). I believe that most of the readers of my blog are already familiar with Xilinx Zynq® UltraScale …
The reverse engineering of the FPGA accelerator card from eBay is progressing well and documenting the DDR3 interface was a huge step forward. However, there is still one important part of the board which is not fully uncovered, the PCI Express® interface. Hardware Pikes Peak Pikes Peak is a Stratix …
In my last blog post I have presented a method to extract the DDR3 pinout from the bitstream, obtained from the on-board Flash. In this post I will use the information obtained from the bitstream to instantiate a DDR3 memory controller and measure its performance. DDR3 SDRAM Controller with UniPHY …
The last piece of the puzzle on the Stratix V board is the DDR3 memory pinout. Once this is figured out, I can finally start using the board for my developments. It is obvious that this is not the most simple way to get a cheap FPGA development board, but …
In the part 4 of the Odyssey with the Startix V board from the eBay, I explore the QSFP+ port and establish a 40 Gigabit Ethernet connection to a computer with an Intel X710 40GbE network adapter. HW overview Since this board was designed to run in a datacenter, the …
As mentioned in my previous blog post , the next step would be to get the JTAG running in Quaruts. In this blog post I describe how I managed to develop a library as an interface between the FPGA board and Quartus, and demonstrate the developed interface to download the bitstream …
In my previous blog post I have explored the FPGA card I have purchased on eBay, and in this post I will present an adapter card which I have developed. The adapter provides PCI Express connection between a normal card-edge slot and the FPGA card, as well as the access …
A couple of weeks ago @rombik_su in a Twitter thread pointed out a very cheap FPGA accelerator card on eBay. The board contains a proprietary Samtec board-to-board connector, most likely carrying power, PCI Express, and auxiliary signals (JTAG, IPMI to BMC, ...), two QSFP cages, DDR3 and a large FPGA, hidden …
Here are my notes on the book "Synchrotron Radiation Sources: A Primer", edited by H. Winick. Although a little bit dated (the book is from 1995) it gives a nice overview of all components of a modern synchrotron and helps with better understanding of how all subsystem interconnect together. It …
A couple of days ago a new release of Ubuntu, Ubuntu 19.04 Disco Dingo was released. On my personal laptop I follow the non-LTS line, which brings me cool features and updated programs (e.g. Python 3.7, GCC 8.3, ...) out-of-the-box. Unfortunately, because the libraries are updated, the …
I attended FOSDEM 2019 in Brussels: and these are my notes from Quantum Computers, CAD and Open Hardware and Python tracks: Quantum Computing Delivering Practical Quantum Computing on the D-Wave System Intro marketing slide for D-Wave Leap practical = Adiabatic Quantum computer Riggeti uses gate model instead physical impl: 3 m …
Introduction Chisel is a modern take on Hardware Description Languages, such as (System)Verilog and VHDL. Both Verilog and VHDL were conceived in 80s, and are currently still the main two options when it comes to describing hardware. From the Developer Experience point-of-view, I would say that both languages are …
This blog was left dormant for quite some time now. From the last blog post in February 2017 a lot has happened. I have moved to Hamburg, Germany, to start a new position as FPGA Developer at MicroTCA Technology Lab at DESY . This is me in European XFEL tunnel: There …
I am writing this post from Brussels where I am attending FOSDEM 2017 conference. There are a lot of interesting talks, and sometimes it is quite hard to decide on which one to go. Luckily there the talks are recorded and one can later check also the missed ones. Here …
I recently found a great book explaining in details FPGA workflow for Xilinx tools, titled 100 Power Tips for FPGA Designers. Evgeni Stavinov is an experienced FPGA designer who previously worked for Xilinx. It is not evident from the title, but this book focuses almost entirely on the Xilinx, while …
This blog post will show you how one can use the OpenOCD debugger with Altera Cyclone V SoC. Altera Cyclone V SoC is a very interesting integrated circuit, combining dual-core ARM processor and a decent FPGA, allowing a wide variety of possibilities to partition the application between the two. Xilinx …
I have seen this book referenced on several occasions when the software engineering was discussed, but I never had the time to read from first page to the last. I bought the dead-tree version, which gives you a better motivation to read the whole book. Here are my comments and …
Recently I had to implement a parser for the PCIe protocol. The data was captured with Xilinx ChipScope and saved as TSV (tab-separated value) text file. I wanted to implement a parser in Python, my favorite language for this kind of tasks. I have stumbled to a problem when I …
Yesterday I got my Raspberry Pi 2, the evolution of the legendary Raspberry Pi. The evolution is the right word to describe what has changed compared to the previous version. The processor it is now a quad-core, it runs faster, it has got a newer instruction set (ARMv7) and the …
/home/jan/opt/lscc/iCEcube2.2014.12/synpbase/bin/synplify_pro: 186: [: unexpected operator /home/jan/opt/lscc/iCEcube2.2014.12/synpbase/bin/synplify_pro: 200: [: !=: argument expected /home/jan/opt/lscc/iCEcube2.2014.12/synpbase/bin/c_hdl: 186: [: unexpected operator /home/jan/opt/lscc/iCEcube2.2014.12/synpbase/bin/c_hdl: 200 …
As I mentioned in previous post, I started playing around with Lattice iCE40 FPGA. In the last post I did a quick overview of the iCE40 tools. The iCEcube2 cannot compete with Xilinx ISE and Altera Quartus II, not to mention the Vivado, but since this is a low-cost FPGA …
The FPGA market is one of those classical markets where there are two players who have nearly 100% market share, e.g. PC processors (Intel and AMD), graphic cards (NVIDIA and ATI), ... The two mayor players on the FPGA market are Xilinx and Altera. Both of this two companies follows …
During the weekend I was able to take some time to do first test of the theremin. Here are two recordings of my friend Luka playing. There are some more articles explaining how digital theremin works coming, remember to check out my blog.
I just got a Nintendo 64, my friend Rok was kind enough to lend it. I have an interesting project in mind, I will keep you updated. Rok will for sure be the first one to get the alpha version.
Last week I briefly explained how theremin works. I also presented my idea to develop a digital version, using FPGA as a detector of distance between hand and antenna. You have probably already heard a joke about theory and practice. Theory is when you know everything but nothing works. Practice …
Theremin, a first electronic instrument. Leon Theremin invented it in 1928. Try to imagine people seeing somebody waving hand in the middle or the air and producing an extraterrestrial sounds. Theremin, should be considered a true pioneer of electronic music. The operational principle is quite simple, however an good implementation …
Hi and welcome to my blog. This is a "hello world" style post, I am curently testing pelican static blog generator. Since I don't know how much time I will have to manage this blog I prefer that everything is static. If I some day stop writing this blog, at …