Irrational Analysis is heavily invested in the semiconductor industry.
Positions will change over time and are regularly updated.
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All content published on this newsletter is based on public information and independent research conducted since 2011.
This newsletter is not financial advice and readers should always do their own research before investing in any security.
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Bunch of interesting mostly unrelated things happen this week.
Entire writing backlog has been shifted again but for good reasons. Fun interesting topics jumping the queue is neat.
Cerebras Updates
Gen 3.5 Rumors
Disagg Rumors
Andrew Feldman Interrogation Guide
Retarded Children Fight: Wolfspeed vs Navitas
HBF Base Die Spec Analysis
Aeva got something for NPO/CPO…?
Taalas Overview (AMD just bought them.)
AAOI Earnings Call
Tower Earnings Call
Micro-LED Jihad
Trading Account 8/8/25 Snapshot
A certain type of investor is very interested in Cerebras. Been getting a lot of inbound from that crowd.
Managed to get some new information and… its interesting. Mostly this is me extrapolating odd details.
Cerebras has an event coming up this month to launch the next-generation WSE4. Based on what I have heard, this is more of a gen 3.5 than gen 4.
Most of the focus seems to be on power delivery and clocks. Will have full coverage of their event (also don’t wana be mean and spoil it) so will keep this section brief.
The odd detail that has been sort of nagging me is Andrew Feldman bragging to finance people about “doubling the clocks with new power delivery”. The problem is yield, not clock speed. Why is he hyped about this…?
As a reminder, there are three stages of yield.
Defects (does chip function)
Packaging (does chip survive packaging)
Parametric (does chip meet target speed at acceptable voltage and power)
I have modeled Cerebras final yield at 20% (see old posts) and stand by this modeling. Andrew Feldman likes to throw people off by claiming high yield due to defect routing (#1) which is irritating because that is the easy part. My view has always been that 100% of wafers make it past stage 1. They have a nice NoC and lots of spare cores. It really is not difficult to get 100% functional yield.
As for the explanation of the 20% final yield, I had always assumed death happens at stage 2. Wafer cracking, thermal warping and such. At no point did I think parametric yield would be a problem because surely they solved this… there is no way after all these years they did not solve parametric yield… like they had to have enough tuning knobs to deal with this problem… they can’t be this incompetent.
Well…. maybe they never did solve the parametric yield issue. Maybe the way to read into Andrew Feldman’s claims of “doubling the clocks” is they fixed parametric yield and as a side effect can double clocks.
If you don’t have enough voltage domains or sufficiently clean ripple, yea parametric yield will be dogshit. Unstable WSE that cannot be tuned properly.
My naive view on Cerebras disaggregated inference (prefill/decode disagg) is that it is not possible because the latency of WSE I/O is so bad. Publicly they have claimed “< 5 us” which is horrendous dogshit. Programmers generally complain about latency on the order of 100’s of nanoseconds.
But… I frankly don’t even know what prefil and decode is so… let me just publish some cross-referenced rumors and see if anyone emails me better information.
Cerebras Disagg Rumors:
Cerebras+Trainium allegedly going very well?
Cerebras+Blackwell allegedly making progress via assistance by a third-party?
Cerebras+MI450 announcement is apparently fake bullshit? They made the slide at the last minute and have not even started on the engineering work.
Someone please explain to me the I/O (particularly latency) requirements of diagg inference. I have public email at top of every post to fish for useful information and learning opportunities.
Alright finance friends. You have done well repeatedly asking Andrew the same specific questions. Here is a new set.
Tell Andrew I say hi.
Why is clock speed improving?
Is it because new power delivery has cleaner voltage ripple?
Is it because new power delivery has more granular voltage domain control?
Are the yield issues due to packaging issues or parametric yield issues?
If he brings up the damn defect routing shit again just cut him off.
If he claims the yield is good show him my model and ask him to explain how gross margins, COGS, and ASP can make sense while also having good yield.
What is the relative yield improvement expected in the new generation?
Will ASP go up given the higher performance or is all capacity already under contract at the current ASP?
I am including some pictures for the benefit of both sides. Not clear if finance friends or Andrew know what voltage ripple is.
Here are some common wafer maps.
Usually, you tune individual dice. Cerebras might have not been able to do that due to power delivery limitations. Maybe they (+Vicor) figured it out with upcoming generation.
Looking forward to the upcoming event.
SHOW US WHAT U GOT ANDREW FELDMAN.
Wolfspeed filed a lawsuit recently against Navitas. Few people have asked me about this and my response has been “it makes me sad to see two of my favorite retarded children fight.”
Wolfspeed does not sell GaN anything so this seems odd. Let’s take a tour of the six patents explicitly called out in the press release.
First one is on GaN transistors even though Wolfspeed sells no GaN products or substrates or anything. Also this patent is expected to expire in 4 months. Very classy guys.
No idea what these are. Chemistry shit.
Without commenting on legal matters, this patent seems stupid from an engineering perspective.
The final Wolfspeed patent is SiC specific. Good news Wolfspeed friends, all Navitas SiC products are utter dogshit. I think you guys are fine.
I have been very anti HBF in the past and recently started softening my opposition.
We are going to take a look at the HBF base die spec with a fresh perspective, just for the benefit of a particular type of investor who is really interested in flash.
Basically, there is a… special… subset of hedge fund people who really REALLY want HBF to be a thing just so NAND flash market gets epic supply crunch (via trade ratio dynamics) just like DRAM. They claim to care about the technical merits but friends I know what really has you interested.
Initial public spec is 130 pages long but only ~10 pages are interesting. Let’s get started!
We are off to a not-confidence-inspiring start.
Everyone has UCIe 64G PHYs up and running. Within the next ~6-9 months UCIe 64G will be fully qualified and stable. Given that HBF spec just came out, it is fair to assume that HBF base die development will lag UCIe 64G.
So… they did not include UCIe 64G as an option because something else in the system (NAND PHY?) is the limit. And they are so concerned by this limit they made horrendous slow 8G UCIe speed as an official option.
Synchronous host (UCIe) channels might help. Well maybe no given it’s clock forwarded. Never mind.
Traditional NAND controllers (found inside SSD) run hot and have lots of digital logic to run NAND-specific math. Some of that is still here but a big one got cut.
Went to FMS and chatted with the Sandisk employees at the HBF booth. Spent a good 5 minutes probing them on how much heat this base die is going kick out and they gave good answers.
The host has to supply a REFCLK (separate from UCIe clock forwarding) for the NAND PHYs. Generally, I hate spread-spectrum clocking. Enshittifies your clock in exchange for much lower EMI. In this case, seems the NAND PHY is very sensitive to EMI so fine go for it guys.
It’s probably clock forwarded so that explains the trash PPM and jitter specs to an extent.
Overall, these clocking requirements are strange. Would be fun to talk to someone on this.
Spec basically avoids talking about reliability. Great guys all the numbers that matter are product specific. Very helpful. 🤡
Possibly the worst (most unreadable) diagram I have ever seen. You can see the 16 copies of UCIE (64 lanes each) grouped in blocks of four as expected. This is to mitigate crosstalk.
Overall, I am willing to now soften my view from “HBF is garbage and will never work” to “this is a solution looking for a problem that might work but is not optimal or even good”.
Still believe the correct solution is to have a good I/O system and fan-out. Stacking bad. All of the same arguments I made against HBM apply to HBF.
I wrote a joke post on how a lidar shitco called Aeva could get a NPO/CPO laser win using their high-power amplifier (SOA).
Apparently they might be on the path on getting revenue…
My guess is Innolight. High-power laser shortage is really bad everyone. HINT HINT LONG LUMENTUM HINT HINT.
Edit: Somone pinged me as I was writing and confirmed Innolight with suspicion the hyperscaler is Amazon.
Congrats if you made money on this flaming dogshit.
I spoke with Taalas a few months ago (Ljubisa and one other guy who’s name I don’t remember… sorry) and they never had me sign an NDA so lets have some fun.
What Taalas made is super cool and beautiful engineering but with questionable economic value.
The premise is simple. Burn model weights directly into silicon. If you have a new model or updated weights, you have to literally tape-out a new chip.
Imagine you wished for ultra-fast inference using a cursed monkey paw.
The monkey paw grants you this wish, but with terrible consequences/limitations.
I thought the premise was never going to work and told them this. New AI models constantly coming out. The existing ones get updated every week or so with new RL generated weights.
Well.. AMD bought Taalas. Most likely for reasons you don’t expect. Will get to that.
Modern leading-edge (7nm class and below) logic nodes have 14-18 metal layers typically.
Taalas core IP was a trick to encode model weights by editing a very small number of lithography masks in the upper part of the metal stackup.
This leads to very interesting economic consequences.
Normally, it takes a long time for wafers to go from start to finish. It is standard for logic foundries (TSMC, Samsung, Intel) to hold wafers at a particular stage as a courtesy. It is very common for design groups to want some wafers partially finished so edits can be made quickly.
Depending on the scope of the bug, it is often fixable by editing a specific mask layer. The cost for swapping out one mask is much lower than a full new mask set (tapeout).
So… what Taalas is doing is actually quite clever. The time from sending them a model to having chips back is only ~2-3 months which is not terrible. NRE cost also not that bad.
The software tools Taalas had to develop are extra cool. Ljubisa claimed that it only takes one week to verify new model weight encoding. Abstracting a bit (to prevent AMD getting mad), Taalas made some EDA-like tools. More like custom wrappers on existing EDA tools. This custom design flow vastly sped up the unusual challenges presented by Taalas model weight encoding architecture. It reminded me of how FPGA LUT mapping // synthesis tools work, but on a much larger scale at higher performance. Spent a good 20 minutes going back and forth with Ljubisa on this topic because frankly the initial claim seemed unbelievable. He answered my questions confidently with respectable technical detail/rigor.
Leaving the meeting several months ago, I assumed Taalas as an AI inference silicon company would probably fail but might have a chance if someone figures out how to scale LORA (or similar algorithmic strategy for partial weight update).
But Taalas as an IP company (very interesting patents, custom EDA tools, IP blocks for niche use-cases) was promising. Guessed that Altera, AMD/Xilinx, or Lattice would buy them.
Publicly, AMD is marketing this Taalas acquisition as a datacenter AI play but I think its more for FPGA and perhaps some niche embedded AI markets.
This is not a disagg inference solution like Nvidia/Groq.
Been trading in and out of this chaos ticker. Kinda done with it for now. Mostly because of the earnings call.
As a setup, all you need to know is AAOI story is building huge capacity for transceiver production in Sugar Land (who named this town?) Texas.
Nothing else matters. Just ramp 800G and above transceivers with good yield and stock goto moon.
CEO focusing on high-power lasers for CPO/NPO makes me think they in cope mode. I really do not like this.
Saw that live demo at OFC. No mention on what the linewidth is. Lumentum’s live demo had a claim of 0.5 MHz linewidth and Lumentum has shown public phase noise and lineshape data repeatedly.
I don’t believe you, AAOI. Show data publicly.
AAOI CEO is right. All the hyperscalers were already aggressively moving to get rid of Chinese transceiver dependence.
For more info on the optical transceiver attempted ban, go here.
AAOI CEO is right that vast majority of Chinese laser players cannot do 300mW laser for DWDM.
(AAOI also cannot meet this spec. I am calling their bluff on this).
High-power CPO laser market is Broadcom and Lumentum duopoly.
Coherent has nothing.
AAOI has nothing.
SHOW THE FUCKING PHASE NOISE AND LINEWIDTH DATA.
YOU HAVE A PHD YOU KNOW WHAT PLOTS IM ASKING FOR.
THEY LOOK LIKE THIS. YOU CHOOSE TO SPOUT BULLSHIT WITH NO DATA TO BACK IT UP BECAUSE LUMENTUM AND BROADCOM CRUSH YOU AND YOU DONT FUCKING HAVE ANYTHING.
WHAT IS YOUR BETA-SEPERATION EFFECTIVE LINEWIDTH AT FULL POWER, 50C, USING A SMALL-FOOTPRINT SWITCHING-REGULATOR BASED LASER DRIVER?
LINEWIDTH MEASURMENTS USING A EXPENSIVE BULKY LASER DRIVER DONT COUNT. WHAT IS LINEWIDTH USING AN ELSFP-COMPATABLE FOOTPRINT DRIVER?
DONT YOU DARE PUSH THE BULLSHIT INTRINSIC LINEWIDTH NUMBER.
AAOI is also 2-3 years away. 🙃
Coherent maybe 18 months away depending on how stable their MOPA is.
This is for Openlight. Nice feature (add-on PDK) Tower offers. 20mW class lasers and SOA. As InP shortage gets worse, transceivers built on Openlight/Tower hetero process become more attractive due to higher InP area efficiency (in theory if yields good).
Tower content goes up even if you dont need advanced packaging in a particular NPO design. the SiPho PIC is much larger for NPO. Need CWDM/DWDM muxing eventually. Even single-wavelength NPO needs a longer MZI modulator length to get better extinction ratio… probably. On the other hand maybe MZI length goes down to reduce insertion loss but spacing of the modulators expands to reduce thermal crosstalk. Lot of variables to be honest.
A Tower earnings call is not complete without Russell saying weird shit, going wildly off tangent. We love you buddy!
Some background here:
Global Foundries (GloFo) is the primary competitor to Tower.
Recently GloFo has been spouting bullshit and confusing sell-side.
Russell absolutely dunked on them by using waveguide insertion loss as a key metric.
Global Foundries OCI MSA SCALE “platform” is DOGSHIT.
They don’t have anything. Process is utter garbage. Tower crushes them in insertion loss, bandwidth, frequency response smoothness, process control, PDK quality, hybrid integration options, advanced packaging, and customer support.
Good answer lol.
As an aside, expansion of 300mm SiGe capacity was discussed several times. This is for the Semtech/Marvell/Macom’s of the world. TIA, drivers, CTLE, basically discrete amplifiers.
Hyper bullish readthrough for Semtech cause they have the best stuff.
Semianalysis wrote a note that covered micro-LED and micro-VCSEL and the tone, core conclusions, and several technical statements are completely wrong.
Argued with Dylan and the authors on Twitter and you guys are coping and it is necessary to in detail write up my issues with this institutional note.
I hate micro-LED with the fire of a trillion billion gazillion suns. This section is going to be scorched earth against micro-LED, not any particular person/author/firm.
I despise all micro-LED efforts equally and will attack (the content of) anyone who says anything even remotely positive about this hoax fake fucking dogshit technology with equal vigor.
Some collateral damage against friends is unfortunately neccisary.
Before going through the SA note, let’s recap recent micro-VCSEL and micro-LED public demos at OCP in March 2026.
Full coverage here:
Coherent had a nice 106G PAM4 VCSEL NPO demo.
PAM4 you need FEC and my personal bar (from experience) is you need to show at least 1e-9 all lanes at a conference (cherry picked devices, favorable temperature and voltage conditions) to prove the solution is robust enough for real-world mass deployment.
Coherent is not quite there. But its still a great demo that I enjoyed very much. In truth, the optimal VCSEL NPO/CPO datarate is 32-64G NRZ and given these 106G PAM4 results (53 Gbaud) I think Coherent is capable of making an excellent VCSEL NPO/CPO solution at the optimal slow-and-wide datarate range.
Lumentum’s VCSEL NPO demo was not great to be honest.
No BER measurements and I can tell why. These eyes are ugly. They cheezed the settings to hide how ugly but I can zoom in and spot speckle noise from unacceptably high amplitude noise.
This noise is unlikely to be coming from the VCSELS themselves. Instead I believe Lumentum did a bad job on packaging and electrical crosstalk mitigation.
All four of the presented channels are unacceptably bad. Channels 1 and 2 are super bad.
My bar for slow-and-wide is 1e-12 all channels MINIMUM. Ideally you want 1e-14 all channels to have margin. These strict BER requirements are to run no FEC. If your BER is any higher, some light FEC is needed and the bull case for slow-and wide becomes much less attractive.
To my (human) eye (pun intended) I think Lumentum 32G VCSEL NPO demo was running at 1e-9 to 1e-10 depending on the lane. Not good enough but has a path to getting fixed.
Was having a private debate with an engineer in this space on the “optimal” datarate. The reason I give a range of 32G to 64G NRZ is there are valid arguments on both sides.
Slower datarate reduces pressure on the VCSEL and makes driver requirements easier.
Less bias/drive current means lower power and smaller circuits.
However, you need more channels to get the same shoreline density and thus electrical crosstalk becomes a much bigger problem.
So an optics background person wants slower (32G NRZ) while an electrical background person like myself prefers faster (64G NRZ).
The dream is to direct drive via UCIe and include all sidebands and clock forwarding.
Now let’s take a look at the public micro-LED demo by Avicina.
THIS IS COMPLETE DOGSHIT.
Each of the micro-LEDs are running at only 4 G NRZ. Let me zoom in and show you the AVERAGE pre-FEC BER per group of dogshit.
Best group at 7e-9.
Worst group at 7e-5
Typical group at lets call it 1e-7.
This is a disastrous result. Remember, you need MINIMUM 1e-12 on EVERY SINGLE LANE IN EVERY SINGLE GROUP to run no FEC links.
These BER numbers are so bad they would fail super heavy Reed-Solomon RS(544,514) FEC used in 112G/224G PAM4 Ethernet spec.
MediaTek also had a micro-LED “demo” in their private booth that I got a peak at through the doorway that was guarded. You fools cant stop me from standing outside your booth. Idiots.
It was just slides with bullshit claims. Mediatek in a recent EARNINGS CALL discussed how they are working on ring-based SiPho on TSMC COUPE.
THIS SAME EARNINGS CALL TRANSCRIPT HAS NOT A SINGLE MENTION OF LED OR MICRO-LED.
I am hearing Credo micro-LED effort is not going well and they are evaluating micro-VCSEL as pivot. Good!
So with this background, let us go over the Semianalysis note and further bury micro-LED, the Theranos of communication technologies.
One of these is promising and the other is a hoax that will never work.
Way too low. Micro-VCSEL easily 50% cost reduction.
Micro-LED performance is such dogshit that it fails the same FEC that 200G PAM4 links run.
Reach does not care about fiber attach. Micro-VCSEL has a fiber-attach intensity problem so even on short reach CW DFB/SiPho solution makes a lot of sense with very high DWDM. Again, Micro-LED is a bullshit fake technology and you keep putting it in the same sentence as real technologies, giving false credibility.
Chromatic dispersion is an issue. Moderate issue for low-power VCSEL, catastrophic for micro-LED.
This made my head explode and I got into a direct argument with the person who wrote this. Avicina showed disastrous results at 4G modulation literally less than 5 months ago. Why the hell are you repeating bullshit that Avicina claims with little to no pushback? No, you don’t get to take cover with a weak ass cop-out sentence 10 pages later.
Let me use an analogy with some self-deprecation.
I have been obese for well over a decade and have a body fat % of 31%.
If I tell you that my roadmap is to become a body-builder with less than 4% body fat.
You should not believe me.
You should not re-publish these nonsense claims without immediate and aggressive pushback IN THE SAME PARAGRAPH.
A weak ass hedging sentence several pages away does not count. I have the entire note I know what you wrote and I read the entire thing word-by-word three times.
Crosstalk is not the correct term for this. Should have just stuck with beam convergence.
The real issue with micro-LED is catastrophic phase noise. At no point in the SA note did this topic get proper coverage.
LEDs are not coherent light. This means massive phase noise. Avicina was dumb enough to show their live eye diagram at a conference (PECC I think). Saw it live. The worst jitter I have every seen. Almost looked as if the oscilloscope was severely damaged.
THIS IS WHERE THE SPEED LIMIT COMES FROM.
LEDs are fundamentally extremely high phase noise. The entire point of a laser is low phase noise (coherent light).
Avicina (and all other micro-LED losers) are already FAILING BADLY at 4G NRZ. Let’s say some physics or epitaxy breakthrough happens and they double to 8G. That is still too slow! Electrical crosstalk will murder the signal amplitude noise before the micro-LED has a chance to shit all over phase noise.
Range is less than 10M. Chromatic dispersion is far worse than what the Avicena and Claude told you.
Once again bullshit third-party claims are repeated with zero pushback.
Dan, you were at OFC just like me and saw the Avicina live demo. Typical BER is 1e-7.
Because the BER is far higher than the 1e-12 needed for running no-FEC, micro-LED needs a very heavy DSP running extremely heavy FEC.
Catestrphic chromatic dispersion limits reach severely. I am being very generous by saying 10M. In reality this bullshit LED garbage practically can go only 1-2 meter.
LEDs basically do not have linewidth. It’s incoherent light. A vomit of light. Sure technically you can define a 3dB linewidth but there is no point. People measure linewidth of lasers because that is useful information for designing a system.
Micro-LED has disastrous phase noise. The jitter is horrific. Burst errors come from jitter, not amplitude noise! Micro-LED absolutely needs FEC and heavy DSP!
This entire note is structured and has a tone such that micro-LED and micro-VCSEL are somehow comparable and both viable. THIS IS NOT THE CASE.
No this is wrong. The limit is chromatic dispersion and phase noise.
Also wrong. Everyone measures all these things on full arrays. Well at least they should. If anyone showed you guys data with a single emitter they are trying to hide disastrous electrical+thermal+optical crosstalk and should be dis-regarded as frauds.
GR-468 reliability testing (what Lumentum showed) is at assembly level, not individual device level.
Well limiting per lane speed to 4G means lots of TIAs densely packed together and catastrophic electrical crosstalk. Sure the PDs are good. Who cares? PDs need amplification and the amplifiers will obliterate and already noisy signal.
Micro-LED will never exist outside of science projects. Once again, the note treats a hoax technology with the same credibility as a real technology.
Micro-LED and Micro-VCSEL almost same share.
MICRO-LED IS A 0. IT DOES NOT WORK. IT WILL NEVER WORK.
PHASE NOISE IS A DISASTER EVEN AT 4G.
ELECTRICAL CROSSTALK KILLS THE LINK IF SPEED PER LANE IS UNDER 32G.
MICRO-VCSEL IS BETTER IN EVERY WAY EXCEPT COST. BUT IT CAN WORK! IT DOES NOT MATTER HOW CHEAP BROKEN GARBAGE IS.
Bullshit. The tone of the SA note treated a hoax technology and a real technology as almost equal. Any micro-LED share about 0% is offensive. Showing share in 2030 as micro-LED 27% while micro-VCSEL at 35% is utter nonsense.
Pretty happy with things now. Want to add a bit more to Aehr, Wolfspeed, and AXTI but afraid to push leverage more. Prefer to keep at least 10% drawdown buffer in overnight buying power.
Regarding the small Nvidia options position, this is mainly because Gavin Baker has been tweeting strange things. It appears that he is massively long Nvidia and it’s not going well.
I too have lost a lot of money on Nvidia call options this year.
Either Gavin is right and Nvidia will finally go up again or I will lose another $10K in solidarity.
As for my Cerebras position (another Gavin Baker portfolio company lol), I might be bullish if they show real progress at the upcoming event.
The $100K worth of shares are covered (wrote calls against them) cause the options IV is insane and I can make 5% a week. Don’t feel too strongly so if something happens and I get assigned at $250 then great can go buy more AXTI/WOLF/AEHR.
The single share that is not under a covered call is precious. I am an activist investor running a serious campaign against Andrew Feldman.
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