في هذه المقالة أطرح بعض أشهر أنواع التأشيرات التي تتيح العمل والهجرة إلى المملكة المتحدة. تستهدف تلك المقالة العمال العرب الماهرين من خريجي الجامعات. العمل بدوام كامل في المملكة المتحدة يستلزم (في الغالب) نوع من الكفالة تسمى sponsorship [0]، وهي أن تتكفل شركة أو مؤسسة ما بالعمال الأجانب. تلك الكفالة تتضمن دفع بعض المصاريف لإصدار شهادة، وإعلام الـ Home Office. يحدد لكل شركة عدد معين من العمال…
مقدمة في هذه المقالة ألخص خبرتي في الدراسة في المملكة المتحدة وأعطي بعض النصائح والآراء للراغبين في الدراسة هناك. هذه النصائح قائمة على خبرتي بدراسة الماجستير في جامعة يورك والدكتوراة بجامعة كامبريدج بإنجلترا، والعمل هناك بعد ذلك. المقالة تستهدف الطلاب العرب الراغبين في السفر لدراسة الماجستير والدكتوراة بشكل كبير وإن كانت بعض النصائح تنطبق أيضا على الراغبين في دراسة البكالوريوس. نظام التعليم في…
In Brief: New features: A new option to run seL4 in machine mode. Ported seL4 to QEMU's SiFiveU and virt platforms. DTB parsing in seL4 to read and use UARTs when available. Ported seL4 to run on VC707 FPGA Freedom Unleashed platform. Initial Benchmarking support in seL4. Initial sel4bench port that can measure IPC and trap timing. Details: seL4 in Machine mode Enables future virtualization…
I managed to get Freedom Unleashed U500 and Boom synthesized on VC707 FPGA Board. This motivated me to port seL4 to run there and do some microbenchmarking using sel4bench project. Note that the seL4/RISC-V port is still a prototype, yet it can compete with ARM and x86. The results are based on the following tools/revisions: seL4 9.0.1 Release sel4bench Perfomance Webpage (01/06/2018) SiFive's…
Introduction Having the RISC-V 's GCC and Binutils upstream, as well as the increasing popularity and support RISC-V is getting pushed us to upstream RTEMS /RISC-V port, and it is gonna be part of the upcoming major RTEMS release. RTEMS (The Real-Time Executive for Multiprocessor Systems) is a contemporary Real-time embedded OS, started as a project back in 1988. Since then, it has been used in…
Updates (since 03062017) A new unofficial 24062017 release of seL4, libraries and seL4 Tutorials. SMP support, tested on Spike with 2 - 9 cores: seL4 is using a big kernel lock . Only reschedule IPI (set affinity) is provided. Relying on SBI to do other remote operations. SBI doesn't provide VADDR-> ASID -> HART operation. Using tp register to hold per-core IPC buffer addresses. Ported…
Major updates since 2015 - It's now based on seL4's master (rather than experimental) branch, which means it makes use of architecture-independent verified code. - Instead of earlier 32-bit support, it's now based on 64-bit RISC-V. - Compatible with latest RISC-V priv-1.10 and user-2.2/3 specs. - sel4test and libraries are ported and passing 146/146 tests. - Tested on Spike and Rocket Chip on FPGA…
This is a brief update about RTEMS port progress to RISC-V. RTEMS port for RISC-V architecture (currently riscv32) runs Hello World and Ticker (with sim timer), on both Spike simulator and seL4 microkernel (two cores). The github repo of the port is here [1]. There are two BSPs currently: 1) riscv_generic : This BSP is intended to run in Machine mode, and has been tested on Spike. To run it…
It was great to give a talk about my Google Summer of Code project with lowRISC at the fourth instance of ORCONF conference held this year in CERN, Geneva, Switzerland. ORCONF is concerned with open-source digital design hardware and embedded systems, motivated by the great success of open-source software. lowRISC, my GSoC organization, which aims to produce a fully open hardware system, was one…
This post gives instructions how to build seL4 to run on RISC-V targets (currently Spike simulator and Rocket Chip/FPGA). The default, and currently only, application is SOS [1] which is a simple operating system running on top of seL4. This means other simple applications can be developed based on this seL4/RISC-V port. Prerequisites The development environment is Linux, you need the following…
Abstract After running on Spike simulator, seL4 can now run on the latest up-to-date version of Rocket Chip code on FPGA, the first hardware platform that seL4/RISC-V port can run on. Moreover, seL4 runs on the online jor1k emulator [1]. This can be considered as a starting point for both RISC-V and seL4 to experiment some new security-related and/or scalability solutions based on the flexibility…
SOS running on seL4 on RISC-V Abstract Following the first status update of my project (Porting seL4 to RISC-V), this post reveals more updates, most notably, the port is now mature enough to run SOS (Simple Operating System) which is recommended by the seL4 getting started guide [1] [2] to learn about seL4 programming. Given that SOS is used part of an advanced operating system course offered by…
Introduction This year I am participating in GSoC with a new umbrella organization called lowRISC aiming to produce a completely open-source SoC (System-on-Chip). lowRISC is based on the new open RISC-V ISA, designed by UC Berkeley. I'll be performing a complete RISC-V port of the new formally-verified microkernel seL4 . Details The project basically involves working with seL4 and RISC-V. The next…
If you're a QEMU fan, and want to give it a try running RTEMS, then this post is for you. Make sure you've followed all of the previous instructions described here [1] [2] [3]. There are some RTEMS sim scripts you can use that do the magic of running simulators for you (but then you'll have to get sim-scripts repo and run it from there). I won't go through sim-scripts here, just do it manually as…
At this point, you must be enthusiastic enough to see your effort building the toolchain, simulator and RTEMS [1] [2] [3] coming into action, I mean you can now see RTEMS executing literally! or1ksim simulator needs a script file describing the system architecture, peripherals and CPU version and configurations. RTEMS or1ksim BSP is shipped with such a file that you can see at its source…
If you have not followed the previous tutorial posts describing how to set up your development environment, go ahead and do it [1] [2], I'll be waiting for you to come back again to start building RTEMS for OpenRISC as described here. Currently there is only one RTEMS BSP you can build which runs on both or1ksim and QEMU. Now let's begin. 1- Checking out RTEMS source $ cd…
So, assuming you're coming from the previous post [HOWTO] 1- Build or1k-rtems* toolchain via RSB and have already installed the or1k toolchain for RTEMS, then you're ready to build RTEMS. But before that, you need OpenRISC simulator to run RTEMS on; this post illustrates how to get some simulator(s) built. or1ksim or1ksim the the main or1k simulator, and the one that can run Linux and RTEMS. For…
This is the first post of the HOWTO tutorial to illustrate how to setup your development environment and run RTEMS on OpenRISC/or1ksim. Before beginning some environment variables have to be set up assuming that you're using Linux. Most of the instructions here are quoted from RSB page [1] 1- Setup This is where you executables go. $ export PATH=$HOME/development/rtems/4.11/bin:$PATH 2- Create…
Introduction So, once I had heard about Rump kernels [1] from Gedare Bloom (one of RTEMS maintainers), I started to do some research about it, and whether RTEMS can have a support for such a new architecture. Rump kernel is a way to run unmodified NetBSD kernel drivers virtually anywhere. So, for a platform that can support Rump kernels , a developer can just pick up some NetBSD drivers (that have…
It was a great Google Summer of Code instance this year for me working on a project of my interest (Porting RTEMS to OpenRISC), and achieved a good progress. In this post I will give some implementation details about the parts I worked on, and what has been done so far. 1. CPUKIT The main low-level part of the OpenRISC CPU port goes there. The port provides configurations of the CPU there. All of…
This post describes how to build, configure RTEMS to run on or1ksim emulator. Installing the tool-chain is a prerequisite before applying the steps in this post; if you have not already installed them, check out the steps here and do it. Once the tool-chain are installed and seen in the executable path, you may proceed with the following steps. 1- Set up the work space. $ mkdir ~/rtems-dev $ cd…
As introduced before , this year I'm porting RTEMS to OpenRISC 1000 architecture during GSoC program. Other than getting the tool-chain built for RTEMS , the project is mainly about RTEMS kernel. In this post, I'll list the latest updates, concerning RTEMS kernel, that have been achieved so far. The current status is that RTEMS hello and ticker samples can run on or1ksim (see HOTWO build and run…
This post provides two methods of building RTEMS tool-chain for OpenRISC 1000 architecture: 1) building from RSB (RTEMS Source Builder) and 2) building each tool/program separately by downloading official tools' releases and apply our RTEMS specific patches to them. Merely, RSB is responsible for all the stuff including: setting up the environment, downloading releases, applying patches,…
Part of my GSoC project: Porting RTEMS to OpenRISC , I worked on hacking GNU tools to be able to build these tools for RTEMS targeting O penRISC 1000 (AKA OR1K) architecture. These tools include: binutils, GCC and GDB. Besides, I had to work on Newlib port for OR1K since RTEMS depends on it. or1ksim (OR1K main emulator) is also part of the tool-chain. Currently, all the tools are working fine.…
This year (2014) I’m participating in GSoC program with RTEMS . The project—Porting RTEMS to OpenRISC— (as its name indicates) aims to port RTEMS to OpenRISC architecture. Porting a well-known open source RTOS software like RTEMS for a big open source hardware architecture such as OpenRISC would be of useful to both HW and SW communities. The new port will target a broad range of users and fields…