FPGA projects in VHDL. VHDL tutorials. VHDL code snippets. VHDL free books
This is the third part of a series of articles on VHDL arbiters. In the first part , we commented on what a VHDL arbiter is. In the second part , we saw the VHDL code for a fixed-priority VHDL arbiter. When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car next Friday evening. In a typical situation, if…
FPGASite is alive and kicking! (We just changed our website address). The new blog has several new articles and features, in addition to actualizations of articles that were hosted in the past on this website. Examples: A series of articles and projects for Digilent’s Basys 3 board (using an Artix-7 FPGA from Xilinx) New technical articles and code snippets , among them: AXI-Lite registers bank…
Add captio A global FPGA design contest held by Intel and Terasic, starting tomorrow! All FPGA developers can join the contest as teams and compete or join as a community member and vote! "The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global…
This post is now hosted here
Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don't. When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to…
In the first article of this series , we defined what an HW arbiter is. In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter. The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority. The block also has a busy signal. Arbitration of the bus is done only…
This post is now hosted here
Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target. One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file. One problem of the .hex file format is that it is quite unreadable for humans.…
What is an arbiter? What is an arbiter? An arbiter is a very common block used on HW designs. I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one…
The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980's. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an "electronic brain" was born together with the development of modern computers. AI as…
Guinness is a GUI based framework that includes both a training on a GPU, and a bitstream generation for an FPGA using the Xilinx SDSoC. This tool uses the Chainer deep learning framework to train a binarized CNN. Also, it uses optimization techniques for an FPGA implementation. Compared with the conventional FPGA realizations, although the classification accuracy is 6.5% decayed, the performance…
FPGAs and GPUs: a Tour of SETI's Computer Hardware David MacMahon is a research astronomer with Berkeley SETI Research Center. Dave works on several projects at BSRC, including Breakthrough Listen, designing many of the computer systems we use to process data collected from our telescopes. If you've ever been curious what hardware is required to search for ET, check out this tour of Berkeley SETI…
Image Source: Linked In Machine Learning is a hot I+D topic. One of the strategies used in Machine Learning is to learn by means of neural networks. You can get a free introduction to neural networks here . I also warmly recommend Andrew Ng's introductory course to Machine Learning on Coursera . Machine Learning neural networks were inspired by biological neural networks, and are easily applied…
Reusable blocks (Image source: Altium) This whitepaper by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA: FPGA design process Revision control Coding guidelines Scripting automation PCB design for FPGA VHDL capture and simulation (including OS-VVM package) Project Management Design Resources The whitepaper is available here
This post is now hosted here
Hi, In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it. Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As…
"Xilinx announced today that its Spartan-7 family of FPGAs is now available for order and shipping to standard lead times. As a key member of Xilinx's Cost-Optimized Portfolio, this device family is designed to meet the needs of cost-sensitive markets by delivering low cost and low power entry points that are I/O optimized for connectivity with industry leading performance-per-watt" For more…
This page is now hosted here
Dual Tone Multi-Frequency (DTMF) is a method for encoding and decoding up to sixteen digits and special characters to be sent over a voice channel. DTMF was first developed by Bell Systems in United States, for use in push-button dialing telephones (in constrant to prior phones, which had a mechanic rotary dialing system). DTMF is standardized by ITU-T Recommendation Q.23 A DTMF keypad consists of…
In the first part of this tutorial , we commented about the implementation of a single timer. The second part presented the implementation of a register based timers block, In this (third) part of the tutorial we will see a different way to implement the timers block. The timers block is a rather thirsty animal, let's see how many resources it needs for several configurations: Quantity of LUT…
Block RAM memory - Source: Xilinx This post is now hosted here
Adam Taylor is the well known author of the MicroZed Chronicles blog on Xilinx website. His Chronicles have been running for several years, and Adam has already compiled entries from his blog in two books. The first book is offered for free on the FPGARelated website for registered users. This is a partial list of the book contents: Introduction to the Zynq Software environment and configuration…
Image source: Xilinx "Xilinx today announced that its high-performance Xilinx® Virtex® UltraScale+™ FPGAs are available in Amazon Elastic Compute Cloud (Amazon EC2) F1 instances. This instance provides programmable hardware acceleration with FPGAs and enables users to optimize their compute resources for the unique requirements of their workloads... ... F1 instances will be used to solve complex…