Exploring Parallel Computer Architecture with FPGAs
In this post we review the design and history of MX format reduced precision block floating point vector data formats. In the next post, we explore several possible RISC-V composable custom extensions to compute over them. Microsoft team demonstrates a more frugal way to do AI tensor math, rivals unite in support Last month at [ ]
Congratulations to AMD Embedded on its debut of Microblaze V. With RISC-V support now from AMD, Intel, Lattice, MicroSemi, and others, FPGA vendors transition to RISC-V is (almost) complete. Still a few stragglers. Related, here for your possible amusement is my IEEE FCCM 2019 Soft Processors Panel presentation, A Game of Soft Processors: This panel, [ ]
In winter 2022 I reworked our 2019-2022 work-in-progress materials on RISC-V Composable Custom Extensions into the Draft Proposed RISC-V Composable Custom Extensions Specification. We presented a poster (narration) on this work at the 2022 Paris RISC-V Summit. Then we stepped back, to work elsewhere, and waited to see if there were new interest or uptake [ ]
An FPGA is just a clever heap of multiplexers and mux select memory S3GA RTL v1 is now available on our S3GA github repo. A 2000 LUT configuration, implemented with Openlane Here is the first implementation of the S3GA N=2048,M=8,K=4 design, which fits in the efabless Open Shuttle Program s ~10mm2 caravel_user_project area (2.92mm x 3.52mm) for [ ]
Note: this blog post is under construction. This notice will be removed when it is complete. Introduction: a look back at S4GA In winter 2021 I took the first edition of Matthew Venn s superb Zero to ASIC course. My 300x300um project was S4GA: a small simple slow serial FPGA core, targeting ~0.1mm2 of the 130nm [ ]
Next week we have a poster presentation on our ongoing work on Composable Custom Extensions and Custom Function Units for RISC-V at Spring 2022 RISC-V Week in Paris. Note, unfortunately I will not attend. Other contributors will be on site to present and discuss the work. Here is the poster (PDF) and here is the [ ]
Today s The Register article by Agam Shaw, RISC-V takes steps to minimize fragmentation, discusses RISC-V International s efforts to grapple with the RISC-V instruction set architecture s growing pains as its diverse community strives to apply and optimize RISC-V to many different use cases. There is a fundamental tension between development of new RISC-V optional standard extensions [ ]
This week at Hot Chips 31 (2019) I am presenting a status update poster on the work-in-progress GRVI Phalanx Accelerator Kit: 2GRVI Phalanx: Towards Kilocore RISC-V FPGA Accelerators with HBM2 DRAM (PDF). This is the debut of the FPGA-efficient 2GRVI ( too groovy ) RV64I processing element (PE) core, and of Phalanx support for FPGAs with HBM2 [ ]
Today Xilinx announced the new Alveo U50 Data Center Accelerator Card. Press release. Launch presentation. U50 Home. Product Brief. Data Sheet. User Guide. I usually don t blog about FPGA card announcements but this is a big deal. Finally a vendor FPGA card streamlined and focused on pure data + network compute acceleration, with massive bandwidth [ ]
A kilocore processor with a few DDR4 DRAM channels has never made much sense, and so today I am happy to announce that the GRVI Phalanx massively parallel RISC-V accelerator framework is now running on a Xilinx UltraScale+ VU37P FPGA with 8 GB of integrated in-package HBM2 DRAM, on a Xilinx Alveo U280 accelerator card. [ ]