Designing an Ethernet Switch ASIC
Designing the world’s first open source Ethernet switch ASIC. An unmanaged cut-through 3-port 100Mbps switch fabbed on Global Foundries 180 nm.
Tales on the wire
Recent content on Tales on the wire
Latest posts
FCC has sudo rights: new regulation on consumer grade routers.
Discussion on the new regulations imposed by the FCC on consumer grade routers
Until Heat Death Do Us Part
Broadcasting over Ethernet until the heat death of the universe with a custom ASIC, or yet another terrible idea, this time inspired by reddit.
The door out of Tapeout Hell
The Waffle House Tapeout Tradition.
Exceptional engineers
What makes an exceptional engineer?
The hardware isn't broken, the documentation is !
Silicon erratas or how my first analog ASIC is dead before arrival.
Contact
Ugly by Design
An odd to ugly web design.
Floating point from scratch: Hard Mode
Actually building floating point from scratch!
Tentpole Projects
Projects that expand the space of possibility.
Alibaba cloud FPGA: the 200$ Kintex UltraScale+ [Updated]
No documentation, no problem!
Textures of growing up
Description of the texture of my formative years.
Why wait for the AI bubble to pop to tapeout AI accelerators?
On coping with the difficulties of seperating sincere instrests from fenzys.
Two weeks until tapeout
Chronicles of a bad idea. Or how I designed a systolic array with in-silicon debug infrastructure from scratch in under two weeks, and taped it out on Global Foundry 180 nm though a Tiny Tapeout experimental shuttle.
BLAKE2s Hashing Accelerator: A Solo Tapeout Journey
BLAKE2s ASIC implementation targetting the SKY130A process, tapedout with Tiny Tapeout.
Reflexion on mortality
How giants vanish in silience.
Troubleshooting the redstone D2020, part 2
No documentation, no problem - part 2
MoldUDP64 and ITCH testbench
Top level testbench for the ITCH and MoldUPD64 modules.
ITCH RTL implementation
Design of the ITCH module.
Custom STM32H750 embedded development board
Designing a small stm32h750 development board as an anniversary present
Ethernet 10GBASE-R and 40GBASE-R PCS
RTL implementation of the Ethernet Physical Coding Sublayer (PCS) for 10Gb and 40Gb fiber optics.
Troubleshooting the redstone D2020
No documentation, no problem
Hi, I'm Julia
MoldUDP64 RTL implementation
Discussing the design of the current MoldUDP64 module.
AES 128b RTL implementation
Learn more about me and why I am starting this blog.
BLAKE2 RTL implementation
Learn more about me and why I am starting this blog.