Recent content on Domipheus Labs
I posted a small snippet of information on bluesky recently about reviewers comparing upscalers. I have seen outlets compare images rendered with GPUs in different market segments, such as AMD Radeon RX 9070 XT to Nvidia Geforce RTX 5090. I stated if this is done, FPS needs to be limited to be a fair comparison of upscale quality - this post explains the technical reason as to why.
2025 ?, ? Joined stealth startup May 2025. Principal Member of Technical Staff, Core Technology Group, AMD Led development and release of FSR 4; delivered on time to initial schedule, with all performance and compatibility goals met. FSR 4 team part of AMD Next 5% award for contributions to RDNA 4 GPU release. CTG Releases FSR 3.1.4. Parent grants. Patent filings. Left AMD April 2025. 2024 Senior…
Seems it’s a right of passage for any project of this kind that Doom needs ported to it. For me, I wanted it as a more involved benchmark - the likes of Drystone that gets used everywhere is pretty boring. Why have that when you can publish a Doom timedemo score for your fpga? Along the way, we add a cache in front of the DDR3 to increase performance.
Despite playing with my miniSpartan3 board for quite a while, I’d never attempted to write my FPGA designs to the SPI flash on the board. This means that the FPGA board didn’t do anything until I deployed my design onto it manually - quite useless if you were using the board for a real project, and on power-on you needed it to go to work immediately. Turns out though, it is fairly…
One of the things which RPU has done from the start is keep the cpu pipeline very simple. It’s a Fetch, Decode, Execute, [Memory], Writeback pipeline, but it does not run pipelined. Some operations really do require multiple cycles to execute, and in this post we figure out how to add this functionality into the CPU
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Interrupts and exceptions are important events that any CPU needs to handle. The usual definition is that interrupts happen outside of the CPU – timer events, for example. Exceptions occur within…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. For those who follow me on twitter, you’ll have seen my recent tweets regarding Zephyr OS running on RPU. This was a huge amount of work to get running, most of it debugging on the FPGA itself. For…
Recently, Tomasz Mloduchowski posted a popular article on his blog detailing the steps he undertook to get access to the hidden PCIe interface of Raspberry Pi 4: the first Raspberry Pi to include PCIe in its design. After seeing his post, and realizing I was meaning to go buy a Raspberry Pi 4, it just seemed natural to try and replicate his results in the hope of taking it a bit further. I am…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. You may remember after the switch from my own TPU ISA to RISC-V was made, I stated that interrupts were disabled. This was due to requirements for RISC-V style interrupt mechanisms not being…
RISC-V: Designing a RISC-V CPU in VHDL, Part 22: Doom as a benchmark and adding Cache to RPU Designing a RISC-V CPU in VHDL, Part 21: Multi-cycle execute for multiply and divide Designing a RISC-V CPU in VHDL, Part 20: Interrupts and Exceptions Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit…
My blog used to use Google AdSense advertising, but since May 2019 they have been removed. Instead of adverts, you will see links to cancer charities chosen specifically by myself. If my content or code has helped you in any way, I would appreciate it if you considered those charities for donation in the future. All proceeds from previous AdSense payments were donated to Blood Cancer UK/Bloodwise…
I recently discovered an old Level Design portfolio I had made whilst in school circa 2000-2002. This was before I started university and any foray into C/C++ coding. They all have a name watermark in a particularly awful font! I had actually coded windows utility apps before this – in Visual Basic! Maybe I will document those in a future post. For today, here is a list of some maps I…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. In the last part we got to the point where RISC-V code, built with GCC, could run and display text over HDMI and blink LEDs. However, this could only run from the 192KB of Block RAM we initialized…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. It’s finally time – the big deploy onto Digilent’s Arty S7 board. In my previous part, I went over at a high level the changes made to my TPU cpu core in order to make it consume RISC-V. The CPU…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. It’s been a while. Despite the length of time and lack of posts, rest assured a significant amount of progress has been made on my VHDL CPU over the last year. I’ve hinted at that fact multiple…
tl;dr: This post shows that driving DVI-D over an HDMI cable, directly connected to the High Speed Pmod connector of Digilents Arty S7 board, is very much possible- even at high resolution. I’ve been working away on my RISC-V FPGA based computer ‘kit’, which is based on my VHDL CPU: ported to RISC-V. I wanted to get a new development board with faster ram, and found it hard to find boards with…
Motivation In late 2015 I was doing my usual head-scratching about what gifts to get various family members for the holiday season. My wife mentioned making something electronic for my father-in-laws boat, and after a few hours of collecting thoughts came up with an idea: A Raspberry Pi computer, which could be powered off the boats 12v batteries. This computer would have sensors which made sense…
This is an article on porting my VHDL character generator from a Xilinx Spartan6 device to one with a Spartan3. It starts off as a simple port, analyzing device primitive differences and accounting for them in the design. Along the way, there were considerations on how clocks were generated, characteristics of block ram timing, and general algorithmic design. I’ll assume you’ve read the sections…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. It’s finally that time! I have committed the latest TPU VHDL, assembler and ISA to my github repository. Fair warning: The assembler is _horrid_. The VHDL contains a ISE project for the LX25…
The folks over at Scarab Hardware, who make the miniSpartan6+ board I do most of my FPGA tinkering on, kindly provided me with one of their other devices – the miniSpartan3. miniSpartan3 is a smaller board, with less features and a Spartan3 Xilinx FPGA instead of the newer generation Spartan6. However, it is very competitively priced, with the board I received costing only $39 – which is a bargain…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Now we have text-mode HDMI/DVI-D output, it’s about time we started writing more code for TPU. However, we’ve not delved into too much detail yet about the memory subsystem – the part of the puzzle…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Whilst having a pixel-based video output on TPU is great, there is fundamental limitations with regard to resolutions and memory. It’s very hard to convey real information with such a resolution,…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. I’ve been working towards HDMI output on my TPU SOC, and this week I managed to get enough of something to get pixels (very large pixels!) output to the screen. The plan was to map an area of…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. A few weeks ago I was in San Francisco for the Game Developers Conference (GDC). I decided not to take my MiniSpartan6+ board with me, despite wanting to get more work on TPU completed. Bare…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. It’s been a significant amount of time between this post and my last TPU article. A variety of things caused this – mainly working on a few other projects – but also due to an issue I had with TPU…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Part 10 was supposed to be a very big part, with a special surprise of TPU working with a cool peripheral device, but that work is still ongoing. It’s taking a long time to do, mostly due to being…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. This part is heavy going if you’ve not read the previous posts. Byte Addressing TPU currently operates with memory by addressing 16-bit words. It’s a fairly common set-up for custom processors…
I’m still working on my Soft-CPU TPU, but wanted to implement a communications channel for it to use in order to get some form of input and output from it. The easiest way to do this is to use a UART, and connect it to a USB to Serial converter for logic-level asynchronous communications. Knowing that I’m still pretty new to VHDL and working with FPGA systems in general at this level, I decided to…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. We’re at the point now where the CPU can run some more involved examples. The examples we’ve run to date on the simulator have been fairly simple, and more to the point, tailored to what we have…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Memory Operations We already have a small RAM which holds our instruction stream, but our TPU ISA defines memory read and write instructions, and we should get those instructions working. It’s the…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. The last part paved the way for getting this simple CPU self sustaining. This means that the test bench doesn’t feed instructions into the decoder, the CPU itself requests and fetches from a RAM…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. _This is a disclaimer that the VHDL here is probably not the best you will see, but it gets the job done – in the simulator, at least. If you spot any serious errors, or woeful performance gotchas…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. This is a little disclaimer that the VHDL here is probably not the best you will see, but it gets the job done – in the simulator, at least. If you spot any serious errors, or woeful performance…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing! Instruction Set Architecture The Instruction Set Architecture (ISA) of a CPU defines the set of operations that can be performed, and on what data types. It explains timing, restrictions, and…
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing! ISE WebPACK Design Software I’m using the Xilinx ISE WebPack suite of tools for this project. It’s available here for Windows and Linux, for free. Once installed and set up, you can run the project…
Why design my own CPU, with associated ISA, assembler and other tools? Because, I can! Why not? I’ll learn a load of stuff! The above is the fundamental reason for this series of posts. As a software developer, and in particular, a compiler/debugger engineer, you are exposed to low level architectural details, latencies, hazards and of course, hardware bugs. In the past I’ve been part of teams who…
This is the sixth part of a series of posts detailing steps required to get a simple Z80 based computer running, facilitated by a Teensy microcontroller. It’s a bit of fun, fuzing old and new hobbyist technologies. See Part 1, Part 2, Part 3, Part 4, and Part 5, if you’ve missed them. Attempt 1 Making TeensyZ80 run with a faster, asynchronous clock seems a simple change at first, but it’s proving…
This is the fifth part of a series of posts detailing steps required to get a simple Z80 based computer running, facilitated by a Teensy microcontroller. It’s a bit of fun, fuzing old and new hobbyist technologies. See Part 1, Part 2, Part 3 and Part 4 if you’ve missed them. At the moment, whilst running slowly due to the lock-step synchronous nature of the clock driving the Z80 from the Teensy,…
This is the fourth part of a series of posts detailing steps required to get a simple Z80 based computer running, facilitated by a Teensy microcontroller. It’s a bit of fun, fuzing old and new hobbyist technologies. See Part 1, Part 2 and Part 3, if you’ve missed them. I mentioned ‘VRAM’ in the last post, which really was just an area of ram which I specified to the teensy through a port. I’ve now…
This is the third part of a series of posts detailing steps required to get a simple Z80 based computer running, facilitated by a Teensy microcontroller. It’s a bit of fun, fuzing old and new hobbyist technologies. See Part 1 and Part 2, if you’ve missed them. Now we have the base Z80 working, interrupts and a display connected which can be manipulated in a console/terminal fashion using the Z80…
Interrupts. Lovely interrupts. The Z80 has a maskable interrupt, and a non maskable interrupt. The maskable ones having the feature that they can be disabled and enabled from within code. For me, I wanted to implement maskable Mode 2 Interrupts. Mode 2 interrupts are very powerful. They allow an external device to make the Z80 jump to one of 128 possible locations, by putting the lower half of a…
My Teensy Z80 Homebrew Computer A few months ago, I bid on several ‘box of surplus electronic components’ listings on ebay. My lab needed some more components and I saw some of the things I needed in the listing pictures, so thought I’d go for it. I won all of them, at pretty much my lowest bid price, and when I got the boxes was really happy (I paid ~£20 for >£200 of components, most sealed new).…
Any PCB Ive designed has been single sided due to my simple PCB etch process. Ive been using KiCad for schematic designs and decided to try to take a design from schematic through to full PCB layout. KiCad has certainly got a fair share of UI issues, but for me it seems to be holding up for what I need from it – until I needed to put a bridge (or link, whatever you call them) on the board layout.…
This is part 4 of the Pi On The Wall build log, concerning modifications to the enclosure and how everything comes together into its final form factor. Part 3 was about power consumption, and optimizing it for low-power and ultimately low-temperature running. Previous parts can be found at Part 2 and Part 1. The choice to use a standard (for the UK, anyway) footprint for the Pi On The Wall was…
If you missed Part 1 and Part 2, it’s probably best you at least read Part 1 to understand the scope of the project. Part 2 discusses how the hardware is modified to fit into a restrictive enclosure, measuring only 10mm deep. From the start, I wanted to stretch the boundaries of the Pi On The Wall, and therefore, Raspberry Pi power consumption. It seemed like a rather fun exercise. This post…
This is Part 2 of a series of blogs regarding the development of a wall-mounted server based on the Raspberry Pi, featuring WiFi and a colour touchscreen. Part 1 can be found here. The enclosure I’m using, a re-purposed room thermostat casing, places some very tight constraints on the dimensions of the Raspberry Pi and PiTFT board.The plastic used in the case is quite sturdy, and is at least 2mm…
I’ve been working away at an idea I had that seemed too good to sit on, so jumped at it. It’s easier to explain the purpose in an image: I’ve been meaning to set up my Raspberry Pi to monitor the Heatmiser WiFi thermostat I use, as well as being a small home server. I have a standard wall mount plate free in the hall of our house, the sort of thing the above would mount into and be wired direct to…
Still working on my bench power supply, and wanted to move from my 16×2 retro LCD to something a bit more funky, and found these which use the Samsung S6D02A1 chip. 1.8 Inch Serial SPI TFT LCD Display Module With Power IC SD Socket At the time of writing, you can get these from a UK warehouse for £3.30 shipped for a single unit. That’s awesome. However, the comments were quite bad and many people…