The Gate Array News 2026.
The last article of the season: AMD's Vivado 2026.1 licensing drama, Microchip's Hailo acquisition, Altera's Agilex 9 Direct RF-Series, and a post-quantum TPM-FPGA architecture from SEALSQ and Lattice.
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Red Pitaya STEMlab MCP: Giving an AI Agent Control of the Verification Bench
Building an MCP server that lets an AI agent drive a Red Pitaya STEMlab Pro Gen 2 over SCPI, then using it end-to-end to bring up an ADC-to-DAC bandpass filter on a Digilent USB104 A7 — including the hardware bug the agent's digital checks could not catch.
Getting Started with the Forgix Board: Efinix Trion T8 + RP2354
A hands-on introduction to the Forgix board from Adiuvo Engineering and Training: its Efinix Trion T8 + RP2354 architecture, passive-SPI configuration, a drag-and-drop firmware I wrote to replace the host loader tool, and three headless Efinity examples.
Using the Red Pitaya STEMlab 125-14 PRO Gen 2 as an SDR in GNU Radio
Using the Red Pitaya STEMlab 125-14 PRO Gen 2 as a software-defined radio inside GNU Radio with the pavel-demin source and sink blocks, and why undersampling commercial FM at 94.2 MHz hits an analog wall.
Implementing a Single-Precision Floating-Point Biquad on Versal
How to implement a single-precision floating-point biquad IIR filter on the AMD Versal AI Edge, using the DSP58 slices through the Floating-Point IP and chaining five MACC cores on the iWave Global iG-G57D board.
CryptoliteICE: an Open-Source FPGA-Based TRNG
CryptoliteICE is an open-source USB stick TRNG combining a Lattice iCE40UP5K FPGA and an RP2040 microcontroller. The FPGA generates entropy from 32 parallel ring oscillators; the RP2040 applies NIST SP 800-90B health checks and SHA-256 conditioning before delivering verified random bytes over USB.
Building PetaLinux for a Versal-Based Board
Step-by-step guide to building and deploying a PetaLinux image for the iWave iG-G57M Versal SOM, including SD card root filesystem, Ethernet verification, and Jupyter Notebook support.
Exploring Versal ACAP with the iG-G57D Board
A hands-on introduction to Versal ACAP development with the iG-G57D board: the CIPS IP, the AXI NoC, a custom AXI4-Lite peripheral, and remote hardware debugging with a standalone hw_server.
Getting started with Agilex 3 and floating-point DSP operations
First steps with the Intel Agilex 3 FPGA SoC C-Series dev board: Quartus Prime Pro setup, LED blinker, and a three-band floating-point FIR audio crossover using the native FP DSP blocks.
Remote FPGA verification of DSP algorithm using STEMlab 125-14 PRO Gen 2
How to build an automated remote verification setup for analog signal processing in FPGAs, combining a STEMlab 125-14 PRO Gen 2 as signal generator (SCPI) with a Goertzel filter on a Spartan-7 board and a Python script that runs end-to-end tests and generates a Markdown report.