Recent content on blog.dave.tf
UTL comes from FastLanes, and is designed to make delta decoding very data-parallel. However the paper explains the layout in a way I find confusing, so I’m going to try my own explanation here. I’m going to assume that you know what delta encoding is, as well as the basics of SIMD computing. Basic delta encoding/decoding is a fundamentally sequential problem, because computing each…
This is a slightly cleaned up version of something I felt compelled to write recently, for a different audience in a different context. Some thoughts for folks who may be looking at coding agents and the like for the first time.
The Lattice ECP5 is a capable little FPGA, and has good support for open-source synthesis through the Yosys EDA toolchain. However, information on the details of configuring the FPGA’s builtin PLL clocks is a little thin on the ground. I’m going to try and help a little bit with that here. The ECP5 chip contains a handful of PLL modules. Each one takes a clock signal in, and can derive…
The very short version of the clickbait title: if you create TAI64 timestamps and your implementation mimics libtai, then your timestamps are likely not TAI. The rest of this post is an explanation of what’s going on.
If you’ve never read the classic Reflections on Trusting Trust , and you like the idea of being unsettled about the foundations of computing, go have a read. It’s amazing. It details the strange reality that we can’t truly trust most of the software we use today. Over time, the ideas from that speech evolved into an important question for open-source software: do we know for sure…
I recently got a ULX3S FPGA board, and have been playing with it. This post will be a short introduction to getting a fully OSS toolchain up and running to develop for this board, using the Bluespec programming language and the Yosys ecosystem of synthesis and programming tools. The ULX3S is a great little hacking board. Its centerpiece is a Lattice ECP5 FPGA, a very featureful little FPGA. The…
In my quest to write a fast IPv4+6 parser, I wrote a slow-but-I-think-correct parser, to use as a base of comparison. In doing so, I discovered more cursed IP address representations that I was previously unaware of. Let’s explore together!
Recently I had a chat with the excellent Vallery Lancey , about Kubernetes. Specifically, what we would do differently if we built something new, from the ground up, with no regard for compatibility with Kubernetes. I found that conversation so stimulating that I feel the need to write things down, so here we are.
In parts one , two and three , we went from requirements to a honking big Ebay order of various computer parts. Well, they’ve all arrived, and so it’s time to put our machine together.
In parts one and two we went from a list of requirements to a set of constraints on the hardware we’ll need to buy. In this part, we take to Ebay and turn those vague ideas into a concrete parts list!
In part one we got together some requirements, and got a rough idea of the kind of server we’re thinking about. Now it’s time for some napkin math to work out some minimum hardware specs related to the storage on the box.
A friend would like a new NAS, with a combo of features and performance that would normally place them in the $10k+ range for enterprise grade storage. I offered to see what I could do with hardware from Ebay, and I figured I’d write down my thought process for this kind of thing, in case it’s of use to other homelab shoppers.
As I was setting up my new NAS, I got a nasty surprise: psrinfo , Illumos’s command to list processor information, told me that my CPU only has 1 core. The CPU is a Xeon E3-1220v3, which the Intel Ark says is a 4-core processor. What’s going on?
In a marathon of Bryan Cantrill interviews , Bryan wondered out loud why “jumbo” ethernet frames are 9000 bytes. These days, that’s not a particularly jumbo number, and it’s also a bizarre number. Why not a power of two, or at least a nice round 10000?