Goings-on in the FuseSoC project and other Open Source Silicon related news
In the mid 90's I came into contact with the demo scene, and it blew me away. It was amazing to see what people, many of them teenagers like myself, could do with computers and the whole thing about making visuals and music myself was extremely inspiring. But most of all, I was intrigued by the people who managed to do things with extremely limited resources, like the 4k demos. And when I say 4k,…
SERV 1.4 is finally released. Actually, it has been out since October last year but I've been so busy that I never got around to make a proper write-up. So let's see what the latest version of the award-winning SERV, the world's smallest RISC-V CPU brings. Everybody heard, about the QERV Let's start with the big news. As you probably know if you are reading this, one of the major things that makes…
Some time ago I noticed that I had 100000 views on this blog after almost exactly ten years of occasional writing mostly about my own projects like FuseSoC , Edalize , SERV and VeeRwolf , but also about hot simulation takes , incomprehensible EDA standards and what's going on in general in the FOSSi world. Turns out that the next 100000 visitors only needed 18 months to find this corner of the…
It's time again to do one of those yearly retrospectives. Am I early being unusally early this year since the year hasn't even ended yet? Actually.... this one is for 2024. I was supposed to to it in January but...well... life happened. Anyway, this should be fine, right? It's still 2025 so it's still a retrospective of last year. Aiming to keep this one a bit shorter to release it before the…
FuseSoC now supports SPDX for creating SBOMs, making it the first FPGA/ASIC IP management system with native SBOM capabilities. This advancement is crucial for supply chain security in FPGA device products and is essential for CRA compliance. Open source software is key to modern software creation. With its increasing importance, the need grows to track open source parts and their versions in a…
SERV the 1.3th. CPUs will never be the same again "A new SERV version! How much smaller than the last one?" Hate to disappoint you all, but we have now reached the point where the award-winning SERV , the world's smallest RISC-V CPU won't get much smaller. I still sometimes get ideas for how to make it smaller and then spend a week implementing something just to discover that nine out of ten times…
So, this was supposed to be one of those new year retrospectives. It's just that I didn't really find time to write this until now. Still closer to last new year than the next one, so I think it's ok. As usual, this is a round-up of all free and open source silicon, or FOSSi, things I have been involved in over the past year. FOSSi Foundation Beatiful evening in Santa Barbara. What is not seen in…
What's the missing puzzle piece that improves the open source projects used in the services or products you deliver to customers to bring you profit? Read on to find out Over the years I have created some open source projects. In fact, I have created a lot of open source projects. Some of them are seeing very little real-world use but many of them are used by hobbyists and academic institutions…
Making your own RISC-V CPU is a terrible idea. I have said that many times before. There are already a million RISC-V cores out there to choose from, so making another one makes no sense at all. It's kind of the same thing with UARTs. There are probably as many UART cores written as there are people using one. In my opinion, it's much more important to learn how to reuse and contribute to existing…
Sure, it's not a million, but then again I'm not Arianna Huffington. Given how extremely niche these topics are and that blogging has been declared dead for about a decade now (about as long as I have been blogging, come to think of it), I think that a hundred thousand visitors is actually really really good. It's sure is a lot more than I would ever had imagined when I started doing this ten…
2022 is behind us and as usual I'm wrapping up my open source silicon efforts of the past year in a blog post. Hang on...a 2022 retrospective...? In... the end of April?? Yes, I am fully aware that a third of 2023 has already passed, thank you very much, and that it's way too late to write a new year's retrospective. I have just been extremely busy, but I still wanted to get it out of the system.…
Do you know the best way to find out who is using your open source software? Introduce bugs! You will suddenly come in touch with a lot of users you didn't know existed. And let's just say I found out about a lot of new users after the release of FuseSoC 2.1. And with FuseSoC 2.1 having a lot of new features, it's perhaps not too surprising that the odd bug crept in. But enough about that, because…
A new version of Edalize has just been released and I'm taking the opportunity to dust off this old blog by writing a bit about some of the highlights. In case someone is wondering, Edalize is an open-source abstraction library for EDA tools that allow users to make a description of their RTL design once in a format called EDAM (EDA Metadata) and then Edalize can setup a project for any of the 40+…
Making copies of other people's IP is a terrible thing! And it's a really big problem in the EDA world. Oh, I'm not talking about the legal aspects. That's something I happily leave to the lawyers. No, I'm talking about making copies of source code instead of referencing the original code. It's a big problem because suddenly you have two different versions, and the chances that a fix that was done…
As you probably also know by now there is a fully open source ASIC toolchain called OpenLANE + a 130nm PDK from SkyWater Foundries together with a program called OpenMPW which allows anyone to produce ASICs from their open source RTL designs completely for free. And regular readers probably also know that NLNet Foundation has kindly sponsored an Edalize backend for this toolchain, so that users…
Big things sometimes come in small packages. Version 1.2.0 of the award-winning SERV, the world's smallest RISC-V CPU has been released and it's filled to the brim with new features. Historically, focus has always been on size reduction, making it ever smaller, and that has paid off. It's now about half the size of when it was first introduced. But at this point we're not really getting much…
UVM has been a massive success. There's no doubt about that. For the first time it showed the chip industry the benefits of having a common framework. You can hire directly for UVM skills. Vendors provide UVM models for interfacing their IP. There are tools for generating UVM registers and other boilerplate code. There is training available and forums for asking UVM-related questions. But it…
Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like the prevalent feeling was that everyone just wanted it to be over. And now it is over, except for all those damn retrospectives. So, with the risk of opening up some old wounds I would like to take a look at what happened last year in my corner of the free and open source…
Looks like it's time for a new Edalize release. During this development cycle, most of the work has been done under the hood with creating a new internal architecture and refactoring many of the backends. Most of those efforts will bear fruit longer term, but we can already today see the initial work on the flow API, that has been planned for at least two years. We also welcome a new backend for…
One of the main FOSSi projects I've been running the last couple of years is SweRVolf , a FuseSoC -based reference platform for Western Digital's family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here ) so I won't go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both…
Over the past years there has been a revolution in open source silicon. While there have been open source IP cores and open source chip design tooling available for at least 25 years, a lot of this has been disparate efforts. What we see now is that many of these projects are coming together as a tour de force creating a snowball effect of generating more projects and innovations being built from…
It's February 25th 2021 today and you all know what that means! It's time for another FuseSoC release! So what happened since last time? Well, let's find out. First of all, as I mentioned in the 2020 retrospective , most of the work during this development cycle has been done by Philipp Wagner. Thanks Philipp! He wasn't the alone though. This release had in total 11 people contributing code and…
2020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in the light of this. But there will always be good and bad things happening in the world. So let's keep fighting the bad things and for now take look at what happened last year within the amazing world of open source silicon. I will start by mentioning the most significant, but…
Note: This article was originally posted on LinkedIn in December 2019 and was later posted on this blog with a backdated publishing date I will unfortunately not make it to the RISC-V summit this year, but since everyone will be talking about RISC-V this coming week I thought it would be a good opportunity to highlight some of the work I have done this year within RISC-V and FOSSi (Free and open…
FuseSoC 1.9 will have an impact so great that people will divide history into the eras before and after it's release. But before that happens, it's time for a less earth-shattering minor release. Allow me to introduce FuseSoC 1.8.2 Backend separation The biggest feature is also the least visible for most users. A lot of time since the last release was spent on moving stuff around with the ultimate…