Delivering the future two layers at a time
2025.09.13 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent my 30+ year career designing embedded systems using ASICs, FPGAs, and embedded CPUs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here. The previous chapter enhanced the simple [ ]
2025.09.07 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent my 30+ year career designing embedded systems using ASICs, FPGAs, and embedded CPUs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here. The previous chapter introduced a [ ]
2025.09.06 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent my 30+ year career designing embedded systems using ASICs, FPGAs, and embedded CPUs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here. The previous chapter explained RISC-V [ ]
2025.09.01 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent the majority of my 30+ year career designing digital logic circuits in ASICs and FPGAs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here. This chapter explains [ ]
2025.08.31 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent the majority of my 30+ year career designing digital logic circuits in ASICs and FPGAs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here. This chapter explains [ ]
Table of Contents:Part-1 : What are SoCs?Part-2 : History of Modern Computer ArchitecturePart-3 : RISC-V Assembly LanguagePart-4 : RISC-V and the Femto corePart-5 : Femto-CPU Memory AccessPart-6 : Femto-CPU Blinky in CPart-7 : GNU cross-compilerPart-8 : RISC-V and the KianV corePart-9 : RISC-V and the Hazard3 corePart-10 : Segger JTAG DebuggerPart-11 : Example Design [ ]
2024.09.29 : I’m BSEE Kevin Hubbard from Seattle, WA. I design digital logic circuits. My journey started more than 40 years ago designing digital circuit boards. My first was a simple 5V TTL logic plug-in expansion board for my 8-bit Apple ][+ computer as a teenager in the 1980 s. In the 1990 s I eventually transitioned [ ]
2024.09.08 : I’m BSEE Kevin Hubbard from Seattle, WA. I design digital logic chips that are fast, small, low power, and reliable. That s actually the working title for my upcoming book, FPGA Chip Design for Speed, Area, Power, and Reliability . I ve been doing this ( digital chip design ) for more than 30 years and [ ]
2024.08.25 : I’m BSEE Kevin Hubbard from Seattle, WA. When a stranger asks what I do, I typically answer I design computer chips and they usually stare at me blankly. I don t actually work for Nvidia, AMD or even Intel. I use the term computer chips generically for large digital semiconductor chips which is a [ ]
FIFOs ( First-In, First-Out ) 2024.07.21 : I’m BSEE Kevin Hubbard from Seattle, WA. Starting in 1995 with a 0.35µm (350nm) Xilinx 4036XL, I ve spent the majority of my 30+ year career designing digital logic chips ( ASICs and FPGAs ) for embedded systems. It s been amazing watching Moore s Law enable FPGAs to become more [ ]