InstLatX64
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@InstLatX64
x86/x64, SIMD, #AVX512, "Aha!" moments. I have been writing code since 1986.
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My future posts will be published there first, and here only later
Another interesting GCC patch: disabling the memory-form of NDD #Intel #APX instructions. #DiamondRapids is not mentioned, perhaps this is an #ArcticWolf related issue? i386: Add tuning to disable memory-form NDD github.com/gcc-mirror/gcc…
An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag github.com/gcc-mirror/gcc… Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove
An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag github.com/gcc-mirror/gcc… Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove
There are already two working desktop #NovaLake CPUID 300F15 among the #Intel test machines: - 24c/24t 3400 MHz [1] - 28c/28t 3200 MHz [2] #CoyoteCove #ArcticWolf #AVX512 #APX enabled [1]: intel-gfx-ci.01.org/tree/drm-xe-fi… [2]: intel-gfx-ci.01.org/tree/drm-xe-fi…
A new feature was mentioned for #Intel #CoralRapids on the Linux kernel mailing list: APIC timer virtualization lore.kernel.org/lkml/amnPFlSvI…
#Intel 2026+ v082 This is the current state of my attempt to follow the news, I hope I haven't missed anything important GitHub: github.com/InstLatx64/Ins… #NovaLake #RazerLake #TitanLake #HammerLake #DiamondRapids #Dunlow #CoralRapids #TalladegaForest #APX #AVX10_2 #AVX512
This microcode update reveals the first #PantherLakeR stepping: CPUID E0652 winraid.level1techs.com/t/intel-amd-vi…
