1451 const APInt &DemandedElts,
1458 switch (
I->getOpcode()) {
1460 case Instruction::Load:
1465 case Instruction::And:
1471 case Instruction::Or:
1477 case Instruction::Xor:
1483 case Instruction::Mul: {
1490 case Instruction::UDiv: {
1497 case Instruction::SDiv: {
1504 case Instruction::Select: {
1505 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
1513 ComputeForArm(
I->getOperand(1),
false)
1514 .intersectWith(ComputeForArm(
I->getOperand(2),
true));
1517 case Instruction::FPTrunc:
1518 case Instruction::FPExt:
1519 case Instruction::FPToUI:
1520 case Instruction::FPToSI:
1521 case Instruction::SIToFP:
1522 case Instruction::UIToFP:
1524 case Instruction::PtrToInt:
1525 case Instruction::PtrToAddr:
1526 case Instruction::IntToPtr:
1529 case Instruction::ZExt:
1530 case Instruction::Trunc: {
1531 Type *SrcTy =
I->getOperand(0)->getType();
1533 unsigned SrcBitWidth;
1541 assert(SrcBitWidth &&
"SrcBitWidth can't be zero");
1545 Inst && Inst->hasNonNeg() && !
Known.isNegative())
1546 Known.makeNonNegative();
1550 case Instruction::BitCast: {
1551 Type *SrcTy =
I->getOperand(0)->getType();
1552 if (SrcTy->isIntOrPtrTy() &&
1555 !
I->getType()->isVectorTy()) {
1563 V->getType()->isFPOrFPVectorTy()) {
1564 Type *FPType = V->getType()->getScalarType();
1568 Known = Result.toKnownBits(FPType->getFltSemantics());
1575 if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||
1576 !
I->getType()->isIntOrIntVectorTy() ||
1584 unsigned SubBitWidth = SrcVecTy->getScalarSizeInBits();
1600 unsigned SubScale =
BitWidth / SubBitWidth;
1602 for (
unsigned i = 0; i != NumElts; ++i) {
1603 if (DemandedElts[i])
1604 SubDemandedElts.
setBit(i * SubScale);
1608 for (
unsigned i = 0; i != SubScale; ++i) {
1611 unsigned ShiftElt = IsLE ? i : SubScale - 1 - i;
1612 Known.insertBits(KnownSrc, ShiftElt * SubBitWidth);
1618 unsigned SubScale = SubBitWidth /
BitWidth;
1620 APInt SubDemandedElts =
1625 Known.setAllConflict();
1626 for (
unsigned i = 0; i != NumElts; ++i) {
1627 if (DemandedElts[i]) {
1628 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
1631 if (
Known.isUnknown())
1638 case Instruction::SExt: {
1640 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
1649 case Instruction::Shl: {
1653 bool ShAmtNonZero) {
1654 return KnownBits::shl(KnownVal, KnownAmt, NUW, NSW, ShAmtNonZero);
1661 Known.Zero.setLowBits(
C->countr_zero());
1674 Known.Zero.setBitsFrom(
Y + 1);
1678 case Instruction::LShr: {
1681 bool ShAmtNonZero) {
1689 Known.Zero.setHighBits(
C->countl_zero());
1692 case Instruction::AShr: {
1695 bool ShAmtNonZero) {
1702 case Instruction::Sub: {
1709 case Instruction::Add: {
1716 case Instruction::SRem:
1722 case Instruction::URem:
1727 case Instruction::Alloca:
1730 case Instruction::GetElementPtr: {
1737 APInt AccConstIndices(IndexWidth, 0);
1739 auto AddIndexToKnown = [&](
KnownBits IndexBits) {
1748 "Index width can't be larger than pointer width");
1754 for (
unsigned i = 1, e =
I->getNumOperands(); i != e; ++i, ++GTI) {
1756 if (
Known.isUnknown())
1759 Value *Index =
I->getOperand(i);
1770 "Access to structure field must be known at compile time");
1778 AccConstIndices +=
Offset;
1795 CI->getValue().
sextOrTrunc(IndexWidth) * StrideInBytes;
1815 if (!
Known.isUnknown() && !AccConstIndices.
isZero())
1819 case Instruction::PHI: {
1822 Value *R =
nullptr, *L =
nullptr;
1835 case Instruction::LShr:
1836 case Instruction::AShr:
1837 case Instruction::Shl:
1838 case Instruction::UDiv:
1845 case Instruction::URem: {
1858 case Instruction::Shl:
1862 case Instruction::LShr:
1863 case Instruction::UDiv:
1864 case Instruction::URem:
1869 case Instruction::AShr:
1881 case Instruction::Add:
1882 case Instruction::Sub:
1883 case Instruction::And:
1884 case Instruction::Or:
1885 case Instruction::Mul: {
1892 unsigned OpNum =
P->getOperand(0) == R ? 0 : 1;
1893 Instruction *RInst =
P->getIncomingBlock(OpNum)->getTerminator();
1894 Instruction *LInst =
P->getIncomingBlock(1 - OpNum)->getTerminator();
1923 case Instruction::Add: {
1925 Known.makeNonNegative();
1927 Known.makeNegative();
1933 case Instruction::Sub: {
1937 Known.makeNonNegative();
1939 Known.makeNegative();
1944 case Instruction::Mul:
1946 Known.makeNonNegative();
1961 if (
P->getNumIncomingValues() == 0)
1971 Known.setAllConflict();
1972 for (
const Use &U :
P->operands()) {
2007 if ((TrueSucc == CxtPhi->
getParent()) !=
2024 Known2 = KnownUnion;
2032 if (
Known.isUnknown())
2038 case Instruction::Call:
2039 case Instruction::Invoke: {
2049 if (std::optional<ConstantRange>
Range = CB->getRange())
2052 if (
const Value *RV = CB->getReturnedArgOperand()) {
2053 if (RV->getType() ==
I->getType()) {
2060 if (
Known.hasConflict())
2065 switch (
II->getIntrinsicID()) {
2068 case Intrinsic::abs: {
2070 bool IntMinIsPoison =
match(
II->getArgOperand(1),
m_One());
2074 case Intrinsic::bitreverse:
2078 case Intrinsic::bswap:
2082 case Intrinsic::ctlz: {
2088 PossibleLZ = std::min(PossibleLZ,
BitWidth - 1);
2090 Known.Zero.setBitsFrom(LowBits);
2093 case Intrinsic::cttz: {
2099 PossibleTZ = std::min(PossibleTZ,
BitWidth - 1);
2101 Known.Zero.setBitsFrom(LowBits);
2104 case Intrinsic::ctpop: {
2110 Known.Zero.setBitsFrom(LowBits);
2115 case Intrinsic::fshr:
2116 case Intrinsic::fshl: {
2124 Known =
II->getIntrinsicID() == Intrinsic::fshl
2129 case Intrinsic::clmul:
2134 case Intrinsic::pext:
2139 case Intrinsic::pdep:
2144 case Intrinsic::uadd_sat:
2149 case Intrinsic::usub_sat:
2154 case Intrinsic::sadd_sat:
2159 case Intrinsic::ssub_sat:
2165 case Intrinsic::vector_reverse:
2171 case Intrinsic::vector_reduce_and:
2172 case Intrinsic::vector_reduce_or:
2173 case Intrinsic::vector_reduce_umax:
2174 case Intrinsic::vector_reduce_umin:
2175 case Intrinsic::vector_reduce_smax:
2176 case Intrinsic::vector_reduce_smin:
2179 case Intrinsic::vector_reduce_xor: {
2186 bool EvenCnt = VecTy->getElementCount().isKnownEven();
2190 if (VecTy->isScalableTy() || EvenCnt)
2191 Known.One.clearAllBits();
2194 case Intrinsic::vector_reduce_add: {
2199 Known =
Known.reduceAdd(VecTy->getNumElements());
2202 case Intrinsic::umin:
2207 case Intrinsic::umax:
2212 case Intrinsic::smin:
2218 case Intrinsic::smax:
2224 case Intrinsic::ptrmask: {
2227 const Value *Mask =
I->getOperand(1);
2228 Known2 =
KnownBits(Mask->getType()->getScalarSizeInBits());
2234 case Intrinsic::x86_sse2_pmulh_w:
2235 case Intrinsic::x86_avx2_pmulh_w:
2236 case Intrinsic::x86_avx512_pmulh_w_512:
2241 case Intrinsic::x86_sse2_pmulhu_w:
2242 case Intrinsic::x86_avx2_pmulhu_w:
2243 case Intrinsic::x86_avx512_pmulhu_w_512:
2248 case Intrinsic::x86_sse42_crc32_64_64:
2249 Known.Zero.setBitsFrom(32);
2251 case Intrinsic::x86_ssse3_phadd_d_128:
2252 case Intrinsic::x86_ssse3_phadd_w_128:
2253 case Intrinsic::x86_avx2_phadd_d:
2254 case Intrinsic::x86_avx2_phadd_w: {
2256 I, DemandedElts, Q,
Depth,
2262 case Intrinsic::x86_ssse3_phadd_sw_128:
2263 case Intrinsic::x86_avx2_phadd_sw: {
2268 case Intrinsic::x86_ssse3_phsub_d_128:
2269 case Intrinsic::x86_ssse3_phsub_w_128:
2270 case Intrinsic::x86_avx2_phsub_d:
2271 case Intrinsic::x86_avx2_phsub_w: {
2273 I, DemandedElts, Q,
Depth,
2279 case Intrinsic::x86_ssse3_phsub_sw_128:
2280 case Intrinsic::x86_avx2_phsub_sw: {
2285 case Intrinsic::riscv_vsetvli:
2286 case Intrinsic::riscv_vsetvlimax: {
2287 bool HasAVL =
II->getIntrinsicID() == Intrinsic::riscv_vsetvli;
2300 MaxVL = std::min(MaxVL, CI->getZExtValue());
2302 unsigned KnownZeroFirstBit =
Log2_32(MaxVL) + 1;
2304 Known.Zero.setBitsFrom(KnownZeroFirstBit);
2307 case Intrinsic::amdgcn_mbcnt_hi:
2308 case Intrinsic::amdgcn_mbcnt_lo: {
2311 Known.Zero.setBitsFrom(
2312 II->getIntrinsicID() == Intrinsic::amdgcn_mbcnt_lo ? 6 : 5);
2317 case Intrinsic::vscale: {
2318 if (!
II->getParent() || !
II->getFunction())
2324 case Intrinsic::stepvector: {
2326 unsigned MinNumElts = VecTy->getElementCount().getKnownMinValue();
2330 bool Overflow =
false;
2332 if (VecTy->isScalableTy()) {
2333 if (!
II->getParent() || !
II->getFunction())
2337 .
umul_ov(MaxNumElts, Overflow);
2352 case Instruction::ShuffleVector: {
2366 APInt DemandedLHS, DemandedRHS;
2371 Known.setAllConflict();
2372 if (!!DemandedLHS) {
2373 const Value *
LHS = Shuf->getOperand(0);
2376 if (
Known.isUnknown())
2379 if (!!DemandedRHS) {
2380 const Value *
RHS = Shuf->getOperand(1);
2386 case Instruction::InsertElement: {
2391 const Value *Vec =
I->getOperand(0);
2392 const Value *Elt =
I->getOperand(1);
2395 APInt DemandedVecElts = DemandedElts;
2396 bool NeedsElt =
true;
2398 if (CIdx && CIdx->getValue().ult(NumElts)) {
2399 DemandedVecElts.
clearBit(CIdx->getZExtValue());
2400 NeedsElt = DemandedElts[CIdx->getZExtValue()];
2403 Known.setAllConflict();
2407 if (
Known.isUnknown())
2411 if (!DemandedVecElts.
isZero()) {
2417 case Instruction::ExtractElement: {
2420 const Value *Vec =
I->getOperand(0);
2421 const Value *Idx =
I->getOperand(1);
2430 if (CIdx && CIdx->getValue().ult(NumElts))
2435 case Instruction::ExtractValue:
2440 switch (
II->getIntrinsicID()) {
2442 case Intrinsic::uadd_with_overflow:
2443 case Intrinsic::sadd_with_overflow:
2445 true,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2446 false, DemandedElts,
Known, Known2, Q,
Depth);
2448 case Intrinsic::usub_with_overflow:
2449 case Intrinsic::ssub_with_overflow:
2451 false,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2452 false, DemandedElts,
Known, Known2, Q,
Depth);
2454 case Intrinsic::umul_with_overflow:
2455 case Intrinsic::smul_with_overflow:
2457 false, DemandedElts,
Known, Known2, Q,
Depth);
2463 case Instruction::Freeze:
3293 const APInt &DemandedElts,
3296 switch (
I->getOpcode()) {
3297 case Instruction::Alloca:
3299 return I->getType()->getPointerAddressSpace() == 0;
3300 case Instruction::GetElementPtr:
3301 if (
I->getType()->isPointerTy())
3304 case Instruction::BitCast: {
3332 Type *FromTy =
I->getOperand(0)->getType();
3337 case Instruction::IntToPtr:
3346 case Instruction::PtrToAddr:
3350 case Instruction::PtrToInt:
3354 I->getType()->getScalarSizeInBits())
3357 case Instruction::Trunc:
3360 if (TI->hasNoSignedWrap() || TI->hasNoUnsignedWrap())
3366 case Instruction::Xor:
3367 case Instruction::Sub:
3369 I->getOperand(1),
Depth);
3370 case Instruction::Or:
3381 case Instruction::SExt:
3382 case Instruction::ZExt:
3386 case Instruction::Shl: {
3401 case Instruction::LShr:
3402 case Instruction::AShr: {
3412 if (
Known.isNegative())
3432 case Instruction::UDiv:
3433 case Instruction::SDiv: {
3448 if (
I->getOpcode() == Instruction::SDiv) {
3450 XKnown = XKnown.
abs(
false);
3451 YKnown = YKnown.
abs(
false);
3457 return XUgeY && *XUgeY;
3459 case Instruction::Add: {
3469 case Instruction::Mul: {
3475 case Instruction::Select: {
3482 auto SelectArmIsNonZero = [&](
bool IsTrueArm) {
3484 Op = IsTrueArm ?
I->getOperand(1) :
I->getOperand(2);
3502 if (SelectArmIsNonZero(
true) &&
3503 SelectArmIsNonZero(
false))
3507 case Instruction::PHI: {
3518 RecQ.CxtI = PN->getIncomingBlock(U)->getTerminator();
3522 BasicBlock *TrueSucc, *FalseSucc;
3523 if (match(RecQ.CxtI,
3524 m_Br(m_c_ICmp(Pred, m_Specific(U.get()), m_Value(X)),
3525 m_BasicBlock(TrueSucc), m_BasicBlock(FalseSucc)))) {
3527 if ((TrueSucc == PN->getParent()) != (FalseSucc == PN->getParent())) {
3529 if (FalseSucc == PN->getParent())
3530 Pred = CmpInst::getInversePredicate(Pred);
3531 if (cmpExcludesZero(Pred, X))
3539 case Instruction::InsertElement: {
3543 const Value *Vec =
I->getOperand(0);
3544 const Value *Elt =
I->getOperand(1);
3548 APInt DemandedVecElts = DemandedElts;
3549 bool SkipElt =
false;
3551 if (CIdx && CIdx->getValue().ult(NumElts)) {
3552 DemandedVecElts.
clearBit(CIdx->getZExtValue());
3553 SkipElt = !DemandedElts[CIdx->getZExtValue()];
3559 (DemandedVecElts.
isZero() ||
3562 case Instruction::ExtractElement:
3564 const Value *Vec = EEI->getVectorOperand();
3565 const Value *Idx = EEI->getIndexOperand();
3568 unsigned NumElts = VecTy->getNumElements();
3570 if (CIdx && CIdx->getValue().ult(NumElts))
3576 case Instruction::ShuffleVector: {
3580 APInt DemandedLHS, DemandedRHS;
3586 return (DemandedRHS.
isZero() ||
3591 case Instruction::Freeze:
3595 case Instruction::Load: {
3612 case Instruction::ExtractValue: {
3618 case Instruction::Add:
3623 case Instruction::Sub:
3626 case Instruction::Mul:
3629 false,
false,
Depth);
3635 case Instruction::Call:
3636 case Instruction::Invoke: {
3638 if (
I->getType()->isPointerTy()) {
3639 if (
Call->isReturnNonNull())
3647 if (std::optional<ConstantRange>
Range =
Call->getRange()) {
3648 const APInt ZeroValue(
Range->getBitWidth(), 0);
3649 if (!
Range->contains(ZeroValue))
3652 if (
const Value *RV =
Call->getReturnedArgOperand())
3658 switch (
II->getIntrinsicID()) {
3659 case Intrinsic::sshl_sat:
3660 case Intrinsic::ushl_sat:
3661 case Intrinsic::abs:
3662 case Intrinsic::bitreverse:
3663 case Intrinsic::bswap:
3664 case Intrinsic::ctpop:
3668 case Intrinsic::ssub_sat:
3676 case Intrinsic::sadd_sat:
3678 II->getArgOperand(1),
3679 true,
false,
Depth);
3681 case Intrinsic::vector_reverse:
3685 case Intrinsic::vector_reduce_or:
3686 case Intrinsic::vector_reduce_umax:
3687 case Intrinsic::vector_reduce_umin:
3688 case Intrinsic::vector_reduce_smax:
3689 case Intrinsic::vector_reduce_smin:
3691 case Intrinsic::umax:
3692 case Intrinsic::uadd_sat:
3700 case Intrinsic::smax: {
3703 auto IsNonZero = [&](
Value *
Op, std::optional<bool> &OpNonZero,
3705 if (!OpNonZero.has_value())
3706 OpNonZero = OpKnown.isNonZero() ||
3711 std::optional<bool> Op0NonZero, Op1NonZero;
3715 IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known))
3720 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known))
3722 return IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known) &&
3723 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known);
3725 case Intrinsic::smin: {
3741 case Intrinsic::umin:
3744 case Intrinsic::cttz:
3747 case Intrinsic::ctlz:
3750 case Intrinsic::fshr:
3751 case Intrinsic::fshl:
3753 if (
II->getArgOperand(0) ==
II->getArgOperand(1))
3756 case Intrinsic::vscale:
3758 case Intrinsic::experimental_get_vector_length:
3772 return Known.One != 0;
4368 const APInt &DemandedElts,
4370 Type *Ty = V->getType();
4376 FVTy->getNumElements() == DemandedElts.
getBitWidth() &&
4377 "DemandedElt width should equal the fixed vector number of elements");
4380 "DemandedElt width should be 1 for scalars");
4394 unsigned FirstAnswer = 1;
4405 case Instruction::BitCast: {
4406 Value *Src = U->getOperand(0);
4407 Type *SrcTy = Src->getType();
4411 if (!SrcTy->isIntOrIntVectorTy())
4417 if ((SrcBits % TyBits) != 0)
4430 case Instruction::SExt:
4431 Tmp = TyBits - U->getOperand(0)->getType()->getScalarSizeInBits();
4435 case Instruction::SDiv: {
4436 const APInt *Denominator;
4449 return std::min(TyBits, NumBits + Denominator->
logBase2());
4454 case Instruction::SRem: {
4457 const APInt *Denominator;
4478 unsigned ResBits = TyBits - Denominator->
ceilLogBase2();
4479 Tmp = std::max(Tmp, ResBits);
4485 case Instruction::AShr: {
4490 if (ShAmt->
uge(TyBits))
4493 Tmp += ShAmtLimited;
4494 if (Tmp > TyBits) Tmp = TyBits;
4498 case Instruction::Shl: {
4503 if (ShAmt->
uge(TyBits))
4508 ShAmt->
uge(TyBits -
X->getType()->getScalarSizeInBits())) {
4510 Tmp += TyBits -
X->getType()->getScalarSizeInBits();
4514 if (ShAmt->
uge(Tmp))
4521 case Instruction::And:
4522 case Instruction::Or:
4523 case Instruction::Xor:
4528 FirstAnswer = std::min(Tmp, Tmp2);
4535 case Instruction::Select: {
4539 const APInt *CLow, *CHigh;
4547 return std::min(Tmp, Tmp2);
4550 case Instruction::Add:
4554 if (Tmp == 1)
break;
4558 if (CRHS->isAllOnesValue()) {
4564 if ((
Known.Zero | 1).isAllOnes())
4569 if (
Known.isNonNegative())
4576 return std::min(Tmp, Tmp2) - 1;
4578 case Instruction::Sub:
4585 if (CLHS->isNullValue()) {
4590 if ((
Known.Zero | 1).isAllOnes())
4596 if (
Known.isNonNegative())
4607 return std::min(Tmp, Tmp2) - 1;
4609 case Instruction::Mul: {
4612 unsigned SignBitsOp0 =
4614 if (SignBitsOp0 == 1)
4616 unsigned SignBitsOp1 =
4618 if (SignBitsOp1 == 1)
4620 unsigned OutValidBits =
4621 (TyBits - SignBitsOp0 + 1) + (TyBits - SignBitsOp1 + 1);
4622 return OutValidBits > TyBits ? 1 : TyBits - OutValidBits + 1;
4625 case Instruction::PHI: {
4629 if (NumIncomingValues > 4)
break;
4631 if (NumIncomingValues == 0)
break;
4637 for (
unsigned i = 0, e = NumIncomingValues; i != e; ++i) {
4638 if (Tmp == 1)
return Tmp;
4641 DemandedElts, RecQ,
Depth + 1));
4646 case Instruction::Trunc: {
4651 unsigned OperandTyBits = U->getOperand(0)->getType()->getScalarSizeInBits();
4652 if (Tmp > (OperandTyBits - TyBits))
4653 return Tmp - (OperandTyBits - TyBits);
4658 case Instruction::ExtractElement:
4665 case Instruction::ShuffleVector: {
4673 APInt DemandedLHS, DemandedRHS;
4678 Tmp = std::numeric_limits<unsigned>::max();
4679 if (!!DemandedLHS) {
4680 const Value *
LHS = Shuf->getOperand(0);
4687 if (!!DemandedRHS) {
4688 const Value *
RHS = Shuf->getOperand(1);
4690 Tmp = std::min(Tmp, Tmp2);
4696 assert(Tmp <= TyBits &&
"Failed to determine minimum sign bits");
4699 case Instruction::Call: {
4701 switch (
II->getIntrinsicID()) {
4704 case Intrinsic::abs:
4712 case Intrinsic::smin:
4713 case Intrinsic::smax: {
4714 const APInt *CLow, *CHigh;
4729 if (
unsigned VecSignBits =
4738 return std::max(FirstAnswer,
Known.countMinSignBits());
5169 assert(
Known.isUnknown() &&
"should not be called with known information");
5171 if (!DemandedElts) {
5186 Known.setSignBit(
false);
5192 Known.setSignBit(
false);
5201 bool SignBitAllZero =
true;
5202 bool SignBitAllOne =
true;
5205 unsigned NumElts = VFVTy->getNumElements();
5206 for (
unsigned i = 0; i != NumElts; ++i) {
5207 if (!DemandedElts[i])
5223 const APFloat &
C = CElt->getValueAPF();
5224 Known.KnownFPClasses |=
C.classify();
5226 SignBitAllZero =
false;
5228 SignBitAllOne =
false;
5230 if (SignBitAllOne != SignBitAllZero)
5231 Known.setSignBit(SignBitAllOne);
5237 for (
size_t I = 0,
E = CDS->getNumElements();
I !=
E; ++
I)
5238 Known |= CDS->getElementAsAPFloat(
I).classify();
5245 for (
const Use &
Op : CA->operands()) {
5252 Known |= CFP->getValueAPF().classify();
5260 KnownNotFromFlags |= CB->getRetNoFPClass();
5262 KnownNotFromFlags |= Arg->getNoFPClass();
5266 if (FPOp->hasNoNaNs())
5267 KnownNotFromFlags |=
fcNan;
5268 if (FPOp->hasNoInfs())
5269 KnownNotFromFlags |=
fcInf;
5273 KnownNotFromFlags |= ~AssumedClasses.KnownFPClasses;
5277 InterestedClasses &= ~KnownNotFromFlags;
5280 Known.knownNot(KnownNotFromFlags);
5283 Known.signBitMustBeOne();
5285 Known.signBitMustBeZero();
5296 const unsigned Opc =
Op->getOpcode();
5298 case Instruction::FNeg: {
5304 case Instruction::Select: {
5305 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
5315 ComputeForArm(
Op->getOperand(1),
false)
5316 .intersectWith(ComputeForArm(
Op->getOperand(2),
true));
5319 case Instruction::Load: {
5320 const MDNode *NoFPClass =
5330 case Instruction::Call: {
5334 case Intrinsic::fabs: {
5345 case Intrinsic::copysign: {
5351 KnownSign, Q,
Depth + 1);
5352 Known.copysign(KnownSign);
5355 case Intrinsic::fma:
5356 case Intrinsic::fmuladd: {
5361 if (
II->getArgOperand(0) ==
II->getArgOperand(1)) {
5364 InterestedClasses, KnownAddend, Q,
Depth + 1);
5366 InterestedClasses, KnownSrc, Q,
Depth + 1);
5370 II->getType()->getScalarType()->getFltSemantics();
5374 if (KnownNotFromFlags &
fcNan) {
5379 if (KnownNotFromFlags &
fcInf) {
5389 for (
int I = 0;
I != 3; ++
I) {
5391 InterestedClasses, KnownSrc[
I], Q,
Depth + 1);
5392 if (KnownSrc[
I].isUnknown())
5395 if (KnownNotFromFlags &
fcNan)
5397 if (KnownNotFromFlags &
fcInf)
5403 II->getType()->getScalarType()->getFltSemantics();
5409 case Intrinsic::sqrt:
5410 case Intrinsic::experimental_constrained_sqrt: {
5413 if (InterestedClasses &
fcNan)
5417 KnownSrc, Q,
Depth + 1);
5425 II->getType()->getScalarType()->getFltSemantics();
5435 case Intrinsic::sin: {
5438 KnownSrc, Q,
Depth + 1);
5442 case Intrinsic::cos: {
5445 KnownSrc, Q,
Depth + 1);
5449 case Intrinsic::tan: {
5452 KnownSrc, Q,
Depth + 1);
5456 case Intrinsic::sinh: {
5459 KnownSrc, Q,
Depth + 1);
5463 case Intrinsic::cosh: {
5466 KnownSrc, Q,
Depth + 1);
5470 case Intrinsic::tanh: {
5473 KnownSrc, Q,
Depth + 1);
5477 case Intrinsic::asin: {
5480 KnownSrc, Q,
Depth + 1);
5484 case Intrinsic::acos: {
5487 KnownSrc, Q,
Depth + 1);
5491 case Intrinsic::atan: {
5494 KnownSrc, Q,
Depth + 1);
5498 case Intrinsic::atan2: {
5508 KnownY, Q,
Depth + 1);
5510 KnownX, Q,
Depth + 1);
5514 F ?
F->getDenormalMode(
5515 II->getType()->getScalarType()->getFltSemantics())
5520 case Intrinsic::maxnum:
5521 case Intrinsic::minnum:
5522 case Intrinsic::minimum:
5523 case Intrinsic::maximum:
5524 case Intrinsic::minimumnum:
5525 case Intrinsic::maximumnum: {
5528 KnownLHS, Q,
Depth + 1);
5530 KnownRHS, Q,
Depth + 1);
5535 F ?
F->getDenormalMode(
5536 II->getType()->getScalarType()->getFltSemantics())
5543 case Intrinsic::canonicalize: {
5546 KnownSrc, Q,
Depth + 1);
5550 F ?
F->getDenormalMode(
5551 II->getType()->getScalarType()->getFltSemantics())
5556 case Intrinsic::vector_reduce_fmax:
5557 case Intrinsic::vector_reduce_fmin:
5558 case Intrinsic::vector_reduce_fmaximum:
5559 case Intrinsic::vector_reduce_fminimum:
5560 case Intrinsic::vector_reduce_fmaximumnum:
5561 case Intrinsic::vector_reduce_fminimumnum: {
5565 InterestedClasses, Q,
Depth + 1);
5567 if (!
Known.isKnownNeverNaN())
5568 Known.setSignBit(std::nullopt);
5572 case Intrinsic::vector_reverse:
5575 II->getFastMathFlags(), InterestedClasses, Q,
Depth + 1);
5577 case Intrinsic::trunc:
5578 case Intrinsic::floor:
5579 case Intrinsic::ceil:
5580 case Intrinsic::rint:
5581 case Intrinsic::nearbyint:
5582 case Intrinsic::round:
5583 case Intrinsic::roundeven: {
5591 KnownSrc, Q,
Depth + 1);
5594 KnownSrc, IID == Intrinsic::trunc,
5595 V->getType()->getScalarType()->isMultiUnitFPType());
5598 case Intrinsic::exp:
5599 case Intrinsic::exp2:
5600 case Intrinsic::exp10:
5601 case Intrinsic::amdgcn_exp2: {
5604 KnownSrc, Q,
Depth + 1);
5608 Type *EltTy =
II->getType()->getScalarType();
5609 if (IID == Intrinsic::amdgcn_exp2 && EltTy->
isFloatTy())
5614 case Intrinsic::fptrunc_round: {
5619 case Intrinsic::log:
5620 case Intrinsic::log10:
5621 case Intrinsic::log2:
5622 case Intrinsic::experimental_constrained_log:
5623 case Intrinsic::experimental_constrained_log10:
5624 case Intrinsic::experimental_constrained_log2:
5625 case Intrinsic::amdgcn_log: {
5626 Type *EltTy =
II->getType()->getScalarType();
5641 KnownSrc, Q,
Depth + 1);
5651 case Intrinsic::pow: {
5652 const bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5654 if (!WantNaN && !WantNegative)
5664 InterestedRHS |=
fcNan;
5675 KnownLHS, Q,
Depth + 1);
5684 KnownRHS, Q,
Depth + 1);
5688 case Intrinsic::powi: {
5693 const Value *Exp =
II->getArgOperand(1);
5694 unsigned BitWidth = Exp->getType()->getIntegerBitWidth();
5699 if (InterestedClasses &
fcNan)
5700 InterestedSrcs |=
fcNan;
5701 if (!ExponentKnownBits.
isZero()) {
5702 if (InterestedClasses &
fcInf)
5709 if (InterestedSrcs !=
fcNone)
5711 KnownSrc, Q,
Depth + 1);
5716 case Intrinsic::ldexp: {
5719 KnownSrc, Q,
Depth + 1);
5723 const Value *ExpArg =
II->getArgOperand(1);
5727 : ConstantRange::getFull(
5731 II->getType()->getScalarType()->getFltSemantics();
5741 case Intrinsic::arithmetic_fence: {
5746 case Intrinsic::experimental_constrained_sitofp:
5747 case Intrinsic::experimental_constrained_uitofp:
5757 if (IID == Intrinsic::experimental_constrained_uitofp)
5758 Known.signBitMustBeZero();
5763 case Intrinsic::amdgcn_fract: {
5766 if (InterestedClasses &
fcNan) {
5769 InterestedClasses, KnownSrc, Q,
Depth + 1);
5779 case Intrinsic::amdgcn_rcp: {
5782 KnownSrc, Q,
Depth + 1);
5784 Known.propagateNonNaN(KnownSrc);
5786 Type *EltTy =
II->getType()->getScalarType();
5809 case Intrinsic::amdgcn_rsq: {
5815 KnownSrc, Q,
Depth + 1);
5827 Type *EltTy =
II->getType()->getScalarType();
5847 case Intrinsic::amdgcn_trig_preop: {
5852 case Intrinsic::convert_from_arbitrary_fp: {
5862 II->getType()->getScalarType()->getFltSemantics();
5897 case Instruction::FAdd:
5898 case Instruction::FSub: {
5901 Op->getOpcode() == Instruction::FAdd &&
5903 bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5906 if (!WantNaN && !WantNegative && !WantNegZero)
5912 if (InterestedClasses &
fcNan)
5913 InterestedSrcs |=
fcInf;
5915 KnownRHS, Q,
Depth + 1);
5918 bool Self =
Op->getOperand(0) ==
Op->getOperand(1) &&
5922 KnownLHS = KnownRHS;
5926 WantNegZero ||
Opc == Instruction::FSub) {
5931 Op->getType()->getScalarType()->getFltSemantics();
5935 if (Self &&
Opc == Instruction::FAdd) {
5943 KnownLHS, Q,
Depth + 1);
5954 case Instruction::FMul: {
5957 F ?
F->getDenormalMode(
5958 Op->getType()->getScalarType()->getFltSemantics())
6001 case Instruction::FDiv: {
6002 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
6006 Op->getType()->getScalarType()->getFltSemantics();
6010 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
6029 if (!WantNan && !WantNegative && !WantPositive)
6036 bool KnowSomethingUseful =
6041 if (KnowSomethingUseful)
6048 case Instruction::FRem: {
6049 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
6055 F ?
F->getDenormalMode(
6056 Op->getType()->getScalarType()->getFltSemantics())
6059 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
6078 if (!WantNan && !WantNegative && !WantPositive)
6090 if (KnowSomethingUseful || WantPositive)
6098 case Instruction::FPExt: {
6101 KnownSrc, Q,
Depth + 1);
6104 Op->getType()->getScalarType()->getFltSemantics();
6106 Op->getOperand(0)->getType()->getScalarType()->getFltSemantics();
6111 case Instruction::FPTrunc: {
6116 case Instruction::SIToFP:
6117 case Instruction::UIToFP: {
6128 if (
Op->getOpcode() == Instruction::UIToFP)
6129 Known.signBitMustBeZero();
6142 if (
Op->getOpcode() == Instruction::SIToFP) {
6147 Known.signBitMustBeZero();
6149 Known.signBitMustBeOne();
6154 if (InterestedClasses &
fcInf) {
6159 if (
Op->getOpcode() == Instruction::UIToFP)
6161 else if (
Op->getOpcode() == Instruction::SIToFP)
6166 Type *FPTy =
Op->getType()->getScalarType();
6173 case Instruction::ExtractElement: {
6176 const Value *Vec =
Op->getOperand(0);
6178 APInt DemandedVecElts;
6180 unsigned NumElts = VecTy->getNumElements();
6183 if (CIdx && CIdx->getValue().ult(NumElts))
6186 DemandedVecElts =
APInt(1, 1);
6192 case Instruction::InsertElement: {
6196 const Value *Vec =
Op->getOperand(0);
6197 const Value *Elt =
Op->getOperand(1);
6200 APInt DemandedVecElts = DemandedElts;
6201 bool NeedsElt =
true;
6203 if (CIdx && CIdx->getValue().ult(NumElts)) {
6204 DemandedVecElts.
clearBit(CIdx->getZExtValue());
6205 NeedsElt = DemandedElts[CIdx->getZExtValue()];
6212 if (
Known.isUnknown())
6219 if (!DemandedVecElts.
isZero()) {
6228 case Instruction::ShuffleVector: {
6237 APInt DemandedLHS, DemandedRHS;
6242 if (!!DemandedLHS) {
6243 const Value *
LHS = Shuf->getOperand(0);
6248 if (
Known.isUnknown())
6254 if (!!DemandedRHS) {
6256 const Value *
RHS = Shuf->getOperand(1);
6264 case Instruction::ExtractValue: {
6271 switch (
II->getIntrinsicID()) {
6272 case Intrinsic::frexp: {
6277 InterestedClasses, KnownSrc, Q,
Depth + 1);
6281 Op->getType()->getScalarType()->getFltSemantics();
6298 case Instruction::PHI: {
6301 if (
P->getNumIncomingValues() == 0)
6308 if (
Depth < PhiRecursionLimit) {
6315 for (
const Use &U :
P->operands()) {
6346 if (
P->getNumIncomingValues() != 2 ||
Known.cannotBeOrderedLessThanZero())
6348 for (
unsigned I = 0;
I < 2;
I++) {
6349 Value *RecurValue =
P->getIncomingValue(1 -
I);
6357 switch (
II->getIntrinsicID()) {
6358 case Intrinsic::fma:
6359 case Intrinsic::fmuladd: {
6373 case Instruction::BitCast: {
6376 !Src->getType()->isIntOrIntVectorTy())
6379 const Type *Ty =
Op->getType();
6381 Value *CastLHS, *CastRHS;
6393 Known = KnownLHS | KnownRHS;