1415 const APInt &DemandedElts,
1422 switch (
I->getOpcode()) {
1424 case Instruction::Load:
1429 case Instruction::And:
1435 case Instruction::Or:
1441 case Instruction::Xor:
1447 case Instruction::Mul: {
1454 case Instruction::UDiv: {
1461 case Instruction::SDiv: {
1468 case Instruction::Select: {
1469 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
1477 ComputeForArm(
I->getOperand(1),
false)
1478 .intersectWith(ComputeForArm(
I->getOperand(2),
true));
1481 case Instruction::FPTrunc:
1482 case Instruction::FPExt:
1483 case Instruction::FPToUI:
1484 case Instruction::FPToSI:
1485 case Instruction::SIToFP:
1486 case Instruction::UIToFP:
1488 case Instruction::PtrToInt:
1489 case Instruction::PtrToAddr:
1490 case Instruction::IntToPtr:
1493 case Instruction::ZExt:
1494 case Instruction::Trunc: {
1495 Type *SrcTy =
I->getOperand(0)->getType();
1497 unsigned SrcBitWidth;
1505 assert(SrcBitWidth &&
"SrcBitWidth can't be zero");
1509 Inst && Inst->hasNonNeg() && !
Known.isNegative())
1510 Known.makeNonNegative();
1514 case Instruction::BitCast: {
1515 Type *SrcTy =
I->getOperand(0)->getType();
1516 if (SrcTy->isIntOrPtrTy() &&
1519 !
I->getType()->isVectorTy()) {
1527 V->getType()->isFPOrFPVectorTy()) {
1528 Type *FPType = V->getType()->getScalarType();
1532 Known = Result.toKnownBits(FPType->getFltSemantics());
1539 if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||
1540 !
I->getType()->isIntOrIntVectorTy() ||
1548 unsigned SubBitWidth = SrcVecTy->getScalarSizeInBits();
1564 unsigned SubScale =
BitWidth / SubBitWidth;
1566 for (
unsigned i = 0; i != NumElts; ++i) {
1567 if (DemandedElts[i])
1568 SubDemandedElts.
setBit(i * SubScale);
1572 for (
unsigned i = 0; i != SubScale; ++i) {
1575 unsigned ShiftElt = IsLE ? i : SubScale - 1 - i;
1576 Known.insertBits(KnownSrc, ShiftElt * SubBitWidth);
1582 unsigned SubScale = SubBitWidth /
BitWidth;
1584 APInt SubDemandedElts =
1589 Known.setAllConflict();
1590 for (
unsigned i = 0; i != NumElts; ++i) {
1591 if (DemandedElts[i]) {
1592 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
1595 if (
Known.isUnknown())
1602 case Instruction::SExt: {
1604 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
1613 case Instruction::Shl: {
1617 bool ShAmtNonZero) {
1618 return KnownBits::shl(KnownVal, KnownAmt, NUW, NSW, ShAmtNonZero);
1625 Known.Zero.setLowBits(
C->countr_zero());
1638 Known.Zero.setBitsFrom(
Y + 1);
1642 case Instruction::LShr: {
1645 bool ShAmtNonZero) {
1653 Known.Zero.setHighBits(
C->countl_zero());
1656 case Instruction::AShr: {
1659 bool ShAmtNonZero) {
1666 case Instruction::Sub: {
1673 case Instruction::Add: {
1680 case Instruction::SRem:
1686 case Instruction::URem:
1691 case Instruction::Alloca:
1694 case Instruction::GetElementPtr: {
1701 APInt AccConstIndices(IndexWidth, 0);
1703 auto AddIndexToKnown = [&](
KnownBits IndexBits) {
1712 "Index width can't be larger than pointer width");
1718 for (
unsigned i = 1, e =
I->getNumOperands(); i != e; ++i, ++GTI) {
1720 if (
Known.isUnknown())
1723 Value *Index =
I->getOperand(i);
1734 "Access to structure field must be known at compile time");
1742 AccConstIndices +=
Offset;
1759 CI->getValue().
sextOrTrunc(IndexWidth) * StrideInBytes;
1779 if (!
Known.isUnknown() && !AccConstIndices.
isZero())
1783 case Instruction::PHI: {
1786 Value *R =
nullptr, *L =
nullptr;
1799 case Instruction::LShr:
1800 case Instruction::AShr:
1801 case Instruction::Shl:
1802 case Instruction::UDiv:
1809 case Instruction::URem: {
1822 case Instruction::Shl:
1826 case Instruction::LShr:
1827 case Instruction::UDiv:
1828 case Instruction::URem:
1833 case Instruction::AShr:
1845 case Instruction::Add:
1846 case Instruction::Sub:
1847 case Instruction::And:
1848 case Instruction::Or:
1849 case Instruction::Mul: {
1856 unsigned OpNum =
P->getOperand(0) == R ? 0 : 1;
1857 Instruction *RInst =
P->getIncomingBlock(OpNum)->getTerminator();
1858 Instruction *LInst =
P->getIncomingBlock(1 - OpNum)->getTerminator();
1887 case Instruction::Add: {
1889 Known.makeNonNegative();
1891 Known.makeNegative();
1897 case Instruction::Sub: {
1901 Known.makeNonNegative();
1903 Known.makeNegative();
1908 case Instruction::Mul:
1910 Known.makeNonNegative();
1925 if (
P->getNumIncomingValues() == 0)
1935 Known.setAllConflict();
1936 for (
const Use &U :
P->operands()) {
1971 if ((TrueSucc == CxtPhi->
getParent()) !=
1988 Known2 = KnownUnion;
1996 if (
Known.isUnknown())
2002 case Instruction::Call:
2003 case Instruction::Invoke: {
2013 if (std::optional<ConstantRange>
Range = CB->getRange())
2016 if (
const Value *RV = CB->getReturnedArgOperand()) {
2017 if (RV->getType() ==
I->getType()) {
2024 if (
Known.hasConflict())
2029 switch (
II->getIntrinsicID()) {
2032 case Intrinsic::abs: {
2034 bool IntMinIsPoison =
match(
II->getArgOperand(1),
m_One());
2038 case Intrinsic::bitreverse:
2042 case Intrinsic::bswap:
2046 case Intrinsic::ctlz: {
2052 PossibleLZ = std::min(PossibleLZ,
BitWidth - 1);
2054 Known.Zero.setBitsFrom(LowBits);
2057 case Intrinsic::cttz: {
2063 PossibleTZ = std::min(PossibleTZ,
BitWidth - 1);
2065 Known.Zero.setBitsFrom(LowBits);
2068 case Intrinsic::ctpop: {
2074 Known.Zero.setBitsFrom(LowBits);
2079 case Intrinsic::fshr:
2080 case Intrinsic::fshl: {
2088 Known =
II->getIntrinsicID() == Intrinsic::fshl
2093 case Intrinsic::clmul:
2098 case Intrinsic::pext:
2103 case Intrinsic::pdep:
2108 case Intrinsic::uadd_sat:
2113 case Intrinsic::usub_sat:
2118 case Intrinsic::sadd_sat:
2123 case Intrinsic::ssub_sat:
2129 case Intrinsic::vector_reverse:
2135 case Intrinsic::vector_reduce_and:
2136 case Intrinsic::vector_reduce_or:
2137 case Intrinsic::vector_reduce_umax:
2138 case Intrinsic::vector_reduce_umin:
2139 case Intrinsic::vector_reduce_smax:
2140 case Intrinsic::vector_reduce_smin:
2143 case Intrinsic::vector_reduce_xor: {
2150 bool EvenCnt = VecTy->getElementCount().isKnownEven();
2154 if (VecTy->isScalableTy() || EvenCnt)
2155 Known.One.clearAllBits();
2158 case Intrinsic::vector_reduce_add: {
2163 Known =
Known.reduceAdd(VecTy->getNumElements());
2166 case Intrinsic::umin:
2171 case Intrinsic::umax:
2176 case Intrinsic::smin:
2182 case Intrinsic::smax:
2188 case Intrinsic::ptrmask: {
2191 const Value *Mask =
I->getOperand(1);
2192 Known2 =
KnownBits(Mask->getType()->getScalarSizeInBits());
2198 case Intrinsic::x86_sse2_pmulh_w:
2199 case Intrinsic::x86_avx2_pmulh_w:
2200 case Intrinsic::x86_avx512_pmulh_w_512:
2205 case Intrinsic::x86_sse2_pmulhu_w:
2206 case Intrinsic::x86_avx2_pmulhu_w:
2207 case Intrinsic::x86_avx512_pmulhu_w_512:
2212 case Intrinsic::x86_sse42_crc32_64_64:
2213 Known.Zero.setBitsFrom(32);
2215 case Intrinsic::x86_ssse3_phadd_d_128:
2216 case Intrinsic::x86_ssse3_phadd_w_128:
2217 case Intrinsic::x86_avx2_phadd_d:
2218 case Intrinsic::x86_avx2_phadd_w: {
2220 I, DemandedElts, Q,
Depth,
2226 case Intrinsic::x86_ssse3_phadd_sw_128:
2227 case Intrinsic::x86_avx2_phadd_sw: {
2232 case Intrinsic::x86_ssse3_phsub_d_128:
2233 case Intrinsic::x86_ssse3_phsub_w_128:
2234 case Intrinsic::x86_avx2_phsub_d:
2235 case Intrinsic::x86_avx2_phsub_w: {
2237 I, DemandedElts, Q,
Depth,
2243 case Intrinsic::x86_ssse3_phsub_sw_128:
2244 case Intrinsic::x86_avx2_phsub_sw: {
2249 case Intrinsic::riscv_vsetvli:
2250 case Intrinsic::riscv_vsetvlimax: {
2251 bool HasAVL =
II->getIntrinsicID() == Intrinsic::riscv_vsetvli;
2264 MaxVL = std::min(MaxVL, CI->getZExtValue());
2266 unsigned KnownZeroFirstBit =
Log2_32(MaxVL) + 1;
2268 Known.Zero.setBitsFrom(KnownZeroFirstBit);
2271 case Intrinsic::amdgcn_mbcnt_hi:
2272 case Intrinsic::amdgcn_mbcnt_lo: {
2275 Known.Zero.setBitsFrom(
2276 II->getIntrinsicID() == Intrinsic::amdgcn_mbcnt_lo ? 6 : 5);
2281 case Intrinsic::vscale: {
2282 if (!
II->getParent() || !
II->getFunction())
2292 case Instruction::ShuffleVector: {
2306 APInt DemandedLHS, DemandedRHS;
2311 Known.setAllConflict();
2312 if (!!DemandedLHS) {
2313 const Value *
LHS = Shuf->getOperand(0);
2316 if (
Known.isUnknown())
2319 if (!!DemandedRHS) {
2320 const Value *
RHS = Shuf->getOperand(1);
2326 case Instruction::InsertElement: {
2331 const Value *Vec =
I->getOperand(0);
2332 const Value *Elt =
I->getOperand(1);
2335 APInt DemandedVecElts = DemandedElts;
2336 bool NeedsElt =
true;
2338 if (CIdx && CIdx->getValue().ult(NumElts)) {
2339 DemandedVecElts.
clearBit(CIdx->getZExtValue());
2340 NeedsElt = DemandedElts[CIdx->getZExtValue()];
2343 Known.setAllConflict();
2347 if (
Known.isUnknown())
2351 if (!DemandedVecElts.
isZero()) {
2357 case Instruction::ExtractElement: {
2360 const Value *Vec =
I->getOperand(0);
2361 const Value *Idx =
I->getOperand(1);
2370 if (CIdx && CIdx->getValue().ult(NumElts))
2375 case Instruction::ExtractValue:
2380 switch (
II->getIntrinsicID()) {
2382 case Intrinsic::uadd_with_overflow:
2383 case Intrinsic::sadd_with_overflow:
2385 true,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2386 false, DemandedElts,
Known, Known2, Q,
Depth);
2388 case Intrinsic::usub_with_overflow:
2389 case Intrinsic::ssub_with_overflow:
2391 false,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2392 false, DemandedElts,
Known, Known2, Q,
Depth);
2394 case Intrinsic::umul_with_overflow:
2395 case Intrinsic::smul_with_overflow:
2397 false, DemandedElts,
Known, Known2, Q,
Depth);
2403 case Instruction::Freeze:
3224 const APInt &DemandedElts,
3227 switch (
I->getOpcode()) {
3228 case Instruction::Alloca:
3230 return I->getType()->getPointerAddressSpace() == 0;
3231 case Instruction::GetElementPtr:
3232 if (
I->getType()->isPointerTy())
3235 case Instruction::BitCast: {
3263 Type *FromTy =
I->getOperand(0)->getType();
3268 case Instruction::IntToPtr:
3277 case Instruction::PtrToAddr:
3281 case Instruction::PtrToInt:
3285 I->getType()->getScalarSizeInBits())
3288 case Instruction::Trunc:
3291 if (TI->hasNoSignedWrap() || TI->hasNoUnsignedWrap())
3297 case Instruction::Xor:
3298 case Instruction::Sub:
3300 I->getOperand(1),
Depth);
3301 case Instruction::Or:
3312 case Instruction::SExt:
3313 case Instruction::ZExt:
3317 case Instruction::Shl: {
3332 case Instruction::LShr:
3333 case Instruction::AShr: {
3343 if (
Known.isNegative())
3363 case Instruction::UDiv:
3364 case Instruction::SDiv: {
3379 if (
I->getOpcode() == Instruction::SDiv) {
3381 XKnown = XKnown.
abs(
false);
3382 YKnown = YKnown.
abs(
false);
3388 return XUgeY && *XUgeY;
3390 case Instruction::Add: {
3400 case Instruction::Mul: {
3406 case Instruction::Select: {
3413 auto SelectArmIsNonZero = [&](
bool IsTrueArm) {
3415 Op = IsTrueArm ?
I->getOperand(1) :
I->getOperand(2);
3433 if (SelectArmIsNonZero(
true) &&
3434 SelectArmIsNonZero(
false))
3438 case Instruction::PHI: {
3449 RecQ.CxtI = PN->getIncomingBlock(U)->getTerminator();
3453 BasicBlock *TrueSucc, *FalseSucc;
3454 if (match(RecQ.CxtI,
3455 m_Br(m_c_ICmp(Pred, m_Specific(U.get()), m_Value(X)),
3456 m_BasicBlock(TrueSucc), m_BasicBlock(FalseSucc)))) {
3458 if ((TrueSucc == PN->getParent()) != (FalseSucc == PN->getParent())) {
3460 if (FalseSucc == PN->getParent())
3461 Pred = CmpInst::getInversePredicate(Pred);
3462 if (cmpExcludesZero(Pred, X))
3470 case Instruction::InsertElement: {
3474 const Value *Vec =
I->getOperand(0);
3475 const Value *Elt =
I->getOperand(1);
3479 APInt DemandedVecElts = DemandedElts;
3480 bool SkipElt =
false;
3482 if (CIdx && CIdx->getValue().ult(NumElts)) {
3483 DemandedVecElts.
clearBit(CIdx->getZExtValue());
3484 SkipElt = !DemandedElts[CIdx->getZExtValue()];
3490 (DemandedVecElts.
isZero() ||
3493 case Instruction::ExtractElement:
3495 const Value *Vec = EEI->getVectorOperand();
3496 const Value *Idx = EEI->getIndexOperand();
3499 unsigned NumElts = VecTy->getNumElements();
3501 if (CIdx && CIdx->getValue().ult(NumElts))
3507 case Instruction::ShuffleVector: {
3511 APInt DemandedLHS, DemandedRHS;
3517 return (DemandedRHS.
isZero() ||
3522 case Instruction::Freeze:
3526 case Instruction::Load: {
3543 case Instruction::ExtractValue: {
3549 case Instruction::Add:
3554 case Instruction::Sub:
3557 case Instruction::Mul:
3560 false,
false,
Depth);
3566 case Instruction::Call:
3567 case Instruction::Invoke: {
3569 if (
I->getType()->isPointerTy()) {
3570 if (
Call->isReturnNonNull())
3578 if (std::optional<ConstantRange>
Range =
Call->getRange()) {
3579 const APInt ZeroValue(
Range->getBitWidth(), 0);
3580 if (!
Range->contains(ZeroValue))
3583 if (
const Value *RV =
Call->getReturnedArgOperand())
3589 switch (
II->getIntrinsicID()) {
3590 case Intrinsic::sshl_sat:
3591 case Intrinsic::ushl_sat:
3592 case Intrinsic::abs:
3593 case Intrinsic::bitreverse:
3594 case Intrinsic::bswap:
3595 case Intrinsic::ctpop:
3599 case Intrinsic::ssub_sat:
3607 case Intrinsic::sadd_sat:
3609 II->getArgOperand(1),
3610 true,
false,
Depth);
3612 case Intrinsic::vector_reverse:
3616 case Intrinsic::vector_reduce_or:
3617 case Intrinsic::vector_reduce_umax:
3618 case Intrinsic::vector_reduce_umin:
3619 case Intrinsic::vector_reduce_smax:
3620 case Intrinsic::vector_reduce_smin:
3622 case Intrinsic::umax:
3623 case Intrinsic::uadd_sat:
3631 case Intrinsic::smax: {
3634 auto IsNonZero = [&](
Value *
Op, std::optional<bool> &OpNonZero,
3636 if (!OpNonZero.has_value())
3637 OpNonZero = OpKnown.isNonZero() ||
3642 std::optional<bool> Op0NonZero, Op1NonZero;
3646 IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known))
3651 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known))
3653 return IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known) &&
3654 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known);
3656 case Intrinsic::smin: {
3672 case Intrinsic::umin:
3675 case Intrinsic::cttz:
3678 case Intrinsic::ctlz:
3681 case Intrinsic::fshr:
3682 case Intrinsic::fshl:
3684 if (
II->getArgOperand(0) ==
II->getArgOperand(1))
3687 case Intrinsic::vscale:
3689 case Intrinsic::experimental_get_vector_length:
3703 return Known.One != 0;
4299 const APInt &DemandedElts,
4301 Type *Ty = V->getType();
4307 FVTy->getNumElements() == DemandedElts.
getBitWidth() &&
4308 "DemandedElt width should equal the fixed vector number of elements");
4311 "DemandedElt width should be 1 for scalars");
4325 unsigned FirstAnswer = 1;
4336 case Instruction::BitCast: {
4337 Value *Src = U->getOperand(0);
4338 Type *SrcTy = Src->getType();
4342 if (!SrcTy->isIntOrIntVectorTy())
4348 if ((SrcBits % TyBits) != 0)
4361 case Instruction::SExt:
4362 Tmp = TyBits - U->getOperand(0)->getType()->getScalarSizeInBits();
4366 case Instruction::SDiv: {
4367 const APInt *Denominator;
4380 return std::min(TyBits, NumBits + Denominator->
logBase2());
4385 case Instruction::SRem: {
4388 const APInt *Denominator;
4409 unsigned ResBits = TyBits - Denominator->
ceilLogBase2();
4410 Tmp = std::max(Tmp, ResBits);
4416 case Instruction::AShr: {
4421 if (ShAmt->
uge(TyBits))
4424 Tmp += ShAmtLimited;
4425 if (Tmp > TyBits) Tmp = TyBits;
4429 case Instruction::Shl: {
4434 if (ShAmt->
uge(TyBits))
4439 ShAmt->
uge(TyBits -
X->getType()->getScalarSizeInBits())) {
4441 Tmp += TyBits -
X->getType()->getScalarSizeInBits();
4445 if (ShAmt->
uge(Tmp))
4452 case Instruction::And:
4453 case Instruction::Or:
4454 case Instruction::Xor:
4459 FirstAnswer = std::min(Tmp, Tmp2);
4466 case Instruction::Select: {
4470 const APInt *CLow, *CHigh;
4478 return std::min(Tmp, Tmp2);
4481 case Instruction::Add:
4485 if (Tmp == 1)
break;
4489 if (CRHS->isAllOnesValue()) {
4495 if ((
Known.Zero | 1).isAllOnes())
4500 if (
Known.isNonNegative())
4507 return std::min(Tmp, Tmp2) - 1;
4509 case Instruction::Sub:
4516 if (CLHS->isNullValue()) {
4521 if ((
Known.Zero | 1).isAllOnes())
4527 if (
Known.isNonNegative())
4538 return std::min(Tmp, Tmp2) - 1;
4540 case Instruction::Mul: {
4543 unsigned SignBitsOp0 =
4545 if (SignBitsOp0 == 1)
4547 unsigned SignBitsOp1 =
4549 if (SignBitsOp1 == 1)
4551 unsigned OutValidBits =
4552 (TyBits - SignBitsOp0 + 1) + (TyBits - SignBitsOp1 + 1);
4553 return OutValidBits > TyBits ? 1 : TyBits - OutValidBits + 1;
4556 case Instruction::PHI: {
4560 if (NumIncomingValues > 4)
break;
4562 if (NumIncomingValues == 0)
break;
4568 for (
unsigned i = 0, e = NumIncomingValues; i != e; ++i) {
4569 if (Tmp == 1)
return Tmp;
4572 DemandedElts, RecQ,
Depth + 1));
4577 case Instruction::Trunc: {
4582 unsigned OperandTyBits = U->getOperand(0)->getType()->getScalarSizeInBits();
4583 if (Tmp > (OperandTyBits - TyBits))
4584 return Tmp - (OperandTyBits - TyBits);
4589 case Instruction::ExtractElement:
4596 case Instruction::ShuffleVector: {
4604 APInt DemandedLHS, DemandedRHS;
4609 Tmp = std::numeric_limits<unsigned>::max();
4610 if (!!DemandedLHS) {
4611 const Value *
LHS = Shuf->getOperand(0);
4618 if (!!DemandedRHS) {
4619 const Value *
RHS = Shuf->getOperand(1);
4621 Tmp = std::min(Tmp, Tmp2);
4627 assert(Tmp <= TyBits &&
"Failed to determine minimum sign bits");
4630 case Instruction::Call: {
4632 switch (
II->getIntrinsicID()) {
4635 case Intrinsic::abs:
4643 case Intrinsic::smin:
4644 case Intrinsic::smax: {
4645 const APInt *CLow, *CHigh;
4660 if (
unsigned VecSignBits =
4669 return std::max(FirstAnswer,
Known.countMinSignBits());
5100 assert(
Known.isUnknown() &&
"should not be called with known information");
5102 if (!DemandedElts) {
5117 Known.SignBit =
false;
5123 Known.SignBit =
false;
5132 bool SignBitAllZero =
true;
5133 bool SignBitAllOne =
true;
5136 unsigned NumElts = VFVTy->getNumElements();
5137 for (
unsigned i = 0; i != NumElts; ++i) {
5138 if (!DemandedElts[i])
5154 const APFloat &
C = CElt->getValueAPF();
5155 Known.KnownFPClasses |=
C.classify();
5157 SignBitAllZero =
false;
5159 SignBitAllOne =
false;
5161 if (SignBitAllOne != SignBitAllZero)
5162 Known.SignBit = SignBitAllOne;
5168 for (
size_t I = 0,
E = CDS->getNumElements();
I !=
E; ++
I)
5169 Known |= CDS->getElementAsAPFloat(
I).classify();
5176 for (
const Use &
Op : CA->operands()) {
5183 Known |= CFP->getValueAPF().classify();
5191 KnownNotFromFlags |= CB->getRetNoFPClass();
5193 KnownNotFromFlags |= Arg->getNoFPClass();
5197 if (FPOp->hasNoNaNs())
5198 KnownNotFromFlags |=
fcNan;
5199 if (FPOp->hasNoInfs())
5200 KnownNotFromFlags |=
fcInf;
5204 KnownNotFromFlags |= ~AssumedClasses.KnownFPClasses;
5208 InterestedClasses &= ~KnownNotFromFlags;
5211 Known.knownNot(KnownNotFromFlags);
5214 Known.signBitMustBeOne();
5216 Known.signBitMustBeZero();
5227 const unsigned Opc =
Op->getOpcode();
5229 case Instruction::FNeg: {
5235 case Instruction::Select: {
5236 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
5246 ComputeForArm(
Op->getOperand(1),
false)
5247 .intersectWith(ComputeForArm(
Op->getOperand(2),
true));
5250 case Instruction::Load: {
5251 const MDNode *NoFPClass =
5261 case Instruction::Call: {
5265 case Intrinsic::fabs: {
5276 case Intrinsic::copysign: {
5282 KnownSign, Q,
Depth + 1);
5283 Known.copysign(KnownSign);
5286 case Intrinsic::fma:
5287 case Intrinsic::fmuladd: {
5292 if (
II->getArgOperand(0) ==
II->getArgOperand(1)) {
5295 InterestedClasses, KnownAddend, Q,
Depth + 1);
5297 InterestedClasses, KnownSrc, Q,
Depth + 1);
5301 II->getType()->getScalarType()->getFltSemantics();
5305 if (KnownNotFromFlags &
fcNan) {
5310 if (KnownNotFromFlags &
fcInf) {
5320 for (
int I = 0;
I != 3; ++
I) {
5322 InterestedClasses, KnownSrc[
I], Q,
Depth + 1);
5323 if (KnownSrc[
I].isUnknown())
5326 if (KnownNotFromFlags &
fcNan)
5328 if (KnownNotFromFlags &
fcInf)
5334 II->getType()->getScalarType()->getFltSemantics();
5340 case Intrinsic::sqrt:
5341 case Intrinsic::experimental_constrained_sqrt: {
5344 if (InterestedClasses &
fcNan)
5348 KnownSrc, Q,
Depth + 1);
5356 II->getType()->getScalarType()->getFltSemantics();
5366 case Intrinsic::sin: {
5369 KnownSrc, Q,
Depth + 1);
5373 case Intrinsic::cos: {
5376 KnownSrc, Q,
Depth + 1);
5380 case Intrinsic::tan: {
5383 KnownSrc, Q,
Depth + 1);
5387 case Intrinsic::sinh: {
5390 KnownSrc, Q,
Depth + 1);
5394 case Intrinsic::cosh: {
5397 KnownSrc, Q,
Depth + 1);
5401 case Intrinsic::tanh: {
5404 KnownSrc, Q,
Depth + 1);
5408 case Intrinsic::asin: {
5411 KnownSrc, Q,
Depth + 1);
5415 case Intrinsic::acos: {
5418 KnownSrc, Q,
Depth + 1);
5422 case Intrinsic::atan: {
5425 KnownSrc, Q,
Depth + 1);
5429 case Intrinsic::atan2: {
5439 KnownY, Q,
Depth + 1);
5441 KnownX, Q,
Depth + 1);
5445 F ?
F->getDenormalMode(
5446 II->getType()->getScalarType()->getFltSemantics())
5451 case Intrinsic::maxnum:
5452 case Intrinsic::minnum:
5453 case Intrinsic::minimum:
5454 case Intrinsic::maximum:
5455 case Intrinsic::minimumnum:
5456 case Intrinsic::maximumnum: {
5459 KnownLHS, Q,
Depth + 1);
5461 KnownRHS, Q,
Depth + 1);
5466 F ?
F->getDenormalMode(
5467 II->getType()->getScalarType()->getFltSemantics())
5474 case Intrinsic::canonicalize: {
5477 KnownSrc, Q,
Depth + 1);
5481 F ?
F->getDenormalMode(
5482 II->getType()->getScalarType()->getFltSemantics())
5487 case Intrinsic::vector_reduce_fmax:
5488 case Intrinsic::vector_reduce_fmin:
5489 case Intrinsic::vector_reduce_fmaximum:
5490 case Intrinsic::vector_reduce_fminimum:
5491 case Intrinsic::vector_reduce_fmaximumnum:
5492 case Intrinsic::vector_reduce_fminimumnum: {
5496 InterestedClasses, Q,
Depth + 1);
5498 if (!
Known.isKnownNeverNaN())
5499 Known.SignBit.reset();
5503 case Intrinsic::vector_reverse:
5506 II->getFastMathFlags(), InterestedClasses, Q,
Depth + 1);
5508 case Intrinsic::trunc:
5509 case Intrinsic::floor:
5510 case Intrinsic::ceil:
5511 case Intrinsic::rint:
5512 case Intrinsic::nearbyint:
5513 case Intrinsic::round:
5514 case Intrinsic::roundeven: {
5522 KnownSrc, Q,
Depth + 1);
5525 KnownSrc, IID == Intrinsic::trunc,
5526 V->getType()->getScalarType()->isMultiUnitFPType());
5529 case Intrinsic::exp:
5530 case Intrinsic::exp2:
5531 case Intrinsic::exp10:
5532 case Intrinsic::amdgcn_exp2: {
5535 KnownSrc, Q,
Depth + 1);
5539 Type *EltTy =
II->getType()->getScalarType();
5540 if (IID == Intrinsic::amdgcn_exp2 && EltTy->
isFloatTy())
5545 case Intrinsic::fptrunc_round: {
5550 case Intrinsic::log:
5551 case Intrinsic::log10:
5552 case Intrinsic::log2:
5553 case Intrinsic::experimental_constrained_log:
5554 case Intrinsic::experimental_constrained_log10:
5555 case Intrinsic::experimental_constrained_log2:
5556 case Intrinsic::amdgcn_log: {
5557 Type *EltTy =
II->getType()->getScalarType();
5572 KnownSrc, Q,
Depth + 1);
5582 case Intrinsic::pow: {
5583 const bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5585 if (!WantNaN && !WantNegative)
5595 InterestedRHS |=
fcNan;
5606 KnownLHS, Q,
Depth + 1);
5615 KnownRHS, Q,
Depth + 1);
5619 case Intrinsic::powi: {
5624 const Value *Exp =
II->getArgOperand(1);
5625 unsigned BitWidth = Exp->getType()->getIntegerBitWidth();
5630 if (InterestedClasses &
fcNan)
5631 InterestedSrcs |=
fcNan;
5632 if (!ExponentKnownBits.
isZero()) {
5633 if (InterestedClasses &
fcInf)
5640 if (InterestedSrcs !=
fcNone)
5642 KnownSrc, Q,
Depth + 1);
5647 case Intrinsic::ldexp: {
5650 KnownSrc, Q,
Depth + 1);
5654 const Value *ExpArg =
II->getArgOperand(1);
5658 : ConstantRange::getFull(
5662 II->getType()->getScalarType()->getFltSemantics();
5672 case Intrinsic::arithmetic_fence: {
5677 case Intrinsic::experimental_constrained_sitofp:
5678 case Intrinsic::experimental_constrained_uitofp:
5688 if (IID == Intrinsic::experimental_constrained_uitofp)
5689 Known.signBitMustBeZero();
5694 case Intrinsic::amdgcn_fract: {
5697 if (InterestedClasses &
fcNan) {
5700 InterestedClasses, KnownSrc, Q,
Depth + 1);
5710 case Intrinsic::amdgcn_rcp: {
5713 KnownSrc, Q,
Depth + 1);
5715 Known.propagateNonNaN(KnownSrc);
5717 Type *EltTy =
II->getType()->getScalarType();
5740 case Intrinsic::amdgcn_rsq: {
5746 KnownSrc, Q,
Depth + 1);
5758 Type *EltTy =
II->getType()->getScalarType();
5778 case Intrinsic::amdgcn_trig_preop: {
5783 case Intrinsic::convert_from_arbitrary_fp: {
5793 II->getType()->getScalarType()->getFltSemantics();
5828 case Instruction::FAdd:
5829 case Instruction::FSub: {
5832 Op->getOpcode() == Instruction::FAdd &&
5834 bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5837 if (!WantNaN && !WantNegative && !WantNegZero)
5843 if (InterestedClasses &
fcNan)
5844 InterestedSrcs |=
fcInf;
5846 KnownRHS, Q,
Depth + 1);
5849 bool Self =
Op->getOperand(0) ==
Op->getOperand(1) &&
5853 KnownLHS = KnownRHS;
5857 WantNegZero ||
Opc == Instruction::FSub) {
5862 Op->getType()->getScalarType()->getFltSemantics();
5866 if (Self &&
Opc == Instruction::FAdd) {
5874 KnownLHS, Q,
Depth + 1);
5885 case Instruction::FMul: {
5888 F ?
F->getDenormalMode(
5889 Op->getType()->getScalarType()->getFltSemantics())
5932 case Instruction::FDiv: {
5933 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
5937 Op->getType()->getScalarType()->getFltSemantics();
5941 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
5960 if (!WantNan && !WantNegative && !WantPositive)
5967 bool KnowSomethingUseful =
5972 if (KnowSomethingUseful)
5979 case Instruction::FRem: {
5980 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
5986 F ?
F->getDenormalMode(
5987 Op->getType()->getScalarType()->getFltSemantics())
5990 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
6009 if (!WantNan && !WantNegative && !WantPositive)
6021 if (KnowSomethingUseful || WantPositive)
6029 case Instruction::FPExt: {
6032 KnownSrc, Q,
Depth + 1);
6035 Op->getType()->getScalarType()->getFltSemantics();
6037 Op->getOperand(0)->getType()->getScalarType()->getFltSemantics();
6042 case Instruction::FPTrunc: {
6047 case Instruction::SIToFP:
6048 case Instruction::UIToFP: {
6059 if (
Op->getOpcode() == Instruction::UIToFP)
6060 Known.signBitMustBeZero();
6073 if (
Op->getOpcode() == Instruction::SIToFP) {
6078 Known.signBitMustBeZero();
6080 Known.signBitMustBeOne();
6085 if (InterestedClasses &
fcInf) {
6090 if (
Op->getOpcode() == Instruction::UIToFP)
6092 else if (
Op->getOpcode() == Instruction::SIToFP)
6097 Type *FPTy =
Op->getType()->getScalarType();
6104 case Instruction::ExtractElement: {
6107 const Value *Vec =
Op->getOperand(0);
6109 APInt DemandedVecElts;
6111 unsigned NumElts = VecTy->getNumElements();
6114 if (CIdx && CIdx->getValue().ult(NumElts))
6117 DemandedVecElts =
APInt(1, 1);
6123 case Instruction::InsertElement: {
6127 const Value *Vec =
Op->getOperand(0);
6128 const Value *Elt =
Op->getOperand(1);
6131 APInt DemandedVecElts = DemandedElts;
6132 bool NeedsElt =
true;
6134 if (CIdx && CIdx->getValue().ult(NumElts)) {
6135 DemandedVecElts.
clearBit(CIdx->getZExtValue());
6136 NeedsElt = DemandedElts[CIdx->getZExtValue()];
6143 if (
Known.isUnknown())
6150 if (!DemandedVecElts.
isZero()) {
6159 case Instruction::ShuffleVector: {
6168 APInt DemandedLHS, DemandedRHS;
6173 if (!!DemandedLHS) {
6174 const Value *
LHS = Shuf->getOperand(0);
6179 if (
Known.isUnknown())
6185 if (!!DemandedRHS) {
6187 const Value *
RHS = Shuf->getOperand(1);
6195 case Instruction::ExtractValue: {
6202 switch (
II->getIntrinsicID()) {
6203 case Intrinsic::frexp: {
6208 InterestedClasses, KnownSrc, Q,
Depth + 1);
6212 Op->getType()->getScalarType()->getFltSemantics();
6229 case Instruction::PHI: {
6232 if (
P->getNumIncomingValues() == 0)
6239 if (
Depth < PhiRecursionLimit) {
6246 for (
const Use &U :
P->operands()) {
6277 if (
P->getNumIncomingValues() != 2 ||
Known.cannotBeOrderedLessThanZero())
6279 for (
unsigned I = 0;
I < 2;
I++) {
6280 Value *RecurValue =
P->getIncomingValue(1 -
I);
6288 switch (
II->getIntrinsicID()) {
6289 case Intrinsic::fma:
6290 case Intrinsic::fmuladd: {
6304 case Instruction::BitCast: {
6307 !Src->getType()->isIntOrIntVectorTy())
6310 const Type *Ty =
Op->getType();
6312 Value *CastLHS, *CastRHS;
6324 Known = KnownLHS | KnownRHS;