1415 const APInt &DemandedElts,
1422 switch (
I->getOpcode()) {
1424 case Instruction::Load:
1429 case Instruction::And:
1435 case Instruction::Or:
1441 case Instruction::Xor:
1447 case Instruction::Mul: {
1454 case Instruction::UDiv: {
1461 case Instruction::SDiv: {
1468 case Instruction::Select: {
1469 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
1477 ComputeForArm(
I->getOperand(1),
false)
1478 .intersectWith(ComputeForArm(
I->getOperand(2),
true));
1481 case Instruction::FPTrunc:
1482 case Instruction::FPExt:
1483 case Instruction::FPToUI:
1484 case Instruction::FPToSI:
1485 case Instruction::SIToFP:
1486 case Instruction::UIToFP:
1488 case Instruction::PtrToInt:
1489 case Instruction::PtrToAddr:
1490 case Instruction::IntToPtr:
1493 case Instruction::ZExt:
1494 case Instruction::Trunc: {
1495 Type *SrcTy =
I->getOperand(0)->getType();
1497 unsigned SrcBitWidth;
1505 assert(SrcBitWidth &&
"SrcBitWidth can't be zero");
1509 Inst && Inst->hasNonNeg() && !
Known.isNegative())
1510 Known.makeNonNegative();
1514 case Instruction::BitCast: {
1515 Type *SrcTy =
I->getOperand(0)->getType();
1516 if (SrcTy->isIntOrPtrTy() &&
1519 !
I->getType()->isVectorTy()) {
1527 V->getType()->isFPOrFPVectorTy()) {
1528 Type *FPType = V->getType()->getScalarType();
1532 Known = Result.toKnownBits(FPType->getFltSemantics());
1539 if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||
1540 !
I->getType()->isIntOrIntVectorTy() ||
1548 unsigned SubBitWidth = SrcVecTy->getScalarSizeInBits();
1564 unsigned SubScale =
BitWidth / SubBitWidth;
1566 for (
unsigned i = 0; i != NumElts; ++i) {
1567 if (DemandedElts[i])
1568 SubDemandedElts.
setBit(i * SubScale);
1572 for (
unsigned i = 0; i != SubScale; ++i) {
1575 unsigned ShiftElt = IsLE ? i : SubScale - 1 - i;
1576 Known.insertBits(KnownSrc, ShiftElt * SubBitWidth);
1582 unsigned SubScale = SubBitWidth /
BitWidth;
1584 APInt SubDemandedElts =
1589 Known.setAllConflict();
1590 for (
unsigned i = 0; i != NumElts; ++i) {
1591 if (DemandedElts[i]) {
1592 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
1595 if (
Known.isUnknown())
1602 case Instruction::SExt: {
1604 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
1613 case Instruction::Shl: {
1617 bool ShAmtNonZero) {
1618 return KnownBits::shl(KnownVal, KnownAmt, NUW, NSW, ShAmtNonZero);
1625 Known.Zero.setLowBits(
C->countr_zero());
1638 Known.Zero.setBitsFrom(
Y + 1);
1642 case Instruction::LShr: {
1645 bool ShAmtNonZero) {
1653 Known.Zero.setHighBits(
C->countl_zero());
1656 case Instruction::AShr: {
1659 bool ShAmtNonZero) {
1666 case Instruction::Sub: {
1673 case Instruction::Add: {
1680 case Instruction::SRem:
1686 case Instruction::URem:
1691 case Instruction::Alloca:
1694 case Instruction::GetElementPtr: {
1701 APInt AccConstIndices(IndexWidth, 0);
1703 auto AddIndexToKnown = [&](
KnownBits IndexBits) {
1712 "Index width can't be larger than pointer width");
1718 for (
unsigned i = 1, e =
I->getNumOperands(); i != e; ++i, ++GTI) {
1720 if (
Known.isUnknown())
1723 Value *Index =
I->getOperand(i);
1734 "Access to structure field must be known at compile time");
1742 AccConstIndices +=
Offset;
1759 CI->getValue().
sextOrTrunc(IndexWidth) * StrideInBytes;
1779 if (!
Known.isUnknown() && !AccConstIndices.
isZero())
1783 case Instruction::PHI: {
1786 Value *R =
nullptr, *L =
nullptr;
1799 case Instruction::LShr:
1800 case Instruction::AShr:
1801 case Instruction::Shl:
1802 case Instruction::UDiv:
1809 case Instruction::URem: {
1822 case Instruction::Shl:
1826 case Instruction::LShr:
1827 case Instruction::UDiv:
1828 case Instruction::URem:
1833 case Instruction::AShr:
1845 case Instruction::Add:
1846 case Instruction::Sub:
1847 case Instruction::And:
1848 case Instruction::Or:
1849 case Instruction::Mul: {
1856 unsigned OpNum =
P->getOperand(0) == R ? 0 : 1;
1857 Instruction *RInst =
P->getIncomingBlock(OpNum)->getTerminator();
1858 Instruction *LInst =
P->getIncomingBlock(1 - OpNum)->getTerminator();
1887 case Instruction::Add: {
1889 Known.makeNonNegative();
1891 Known.makeNegative();
1897 case Instruction::Sub: {
1901 Known.makeNonNegative();
1903 Known.makeNegative();
1908 case Instruction::Mul:
1910 Known.makeNonNegative();
1925 if (
P->getNumIncomingValues() == 0)
1935 Known.setAllConflict();
1936 for (
const Use &U :
P->operands()) {
1971 if ((TrueSucc == CxtPhi->
getParent()) !=
1988 Known2 = KnownUnion;
1996 if (
Known.isUnknown())
2002 case Instruction::Call:
2003 case Instruction::Invoke: {
2013 if (std::optional<ConstantRange>
Range = CB->getRange())
2016 if (
const Value *RV = CB->getReturnedArgOperand()) {
2017 if (RV->getType() ==
I->getType()) {
2024 if (
Known.hasConflict())
2029 switch (
II->getIntrinsicID()) {
2032 case Intrinsic::abs: {
2034 bool IntMinIsPoison =
match(
II->getArgOperand(1),
m_One());
2038 case Intrinsic::bitreverse:
2042 case Intrinsic::bswap:
2046 case Intrinsic::ctlz: {
2052 PossibleLZ = std::min(PossibleLZ,
BitWidth - 1);
2054 Known.Zero.setBitsFrom(LowBits);
2057 case Intrinsic::cttz: {
2063 PossibleTZ = std::min(PossibleTZ,
BitWidth - 1);
2065 Known.Zero.setBitsFrom(LowBits);
2068 case Intrinsic::ctpop: {
2074 Known.Zero.setBitsFrom(LowBits);
2079 case Intrinsic::fshr:
2080 case Intrinsic::fshl: {
2088 Known =
II->getIntrinsicID() == Intrinsic::fshl
2093 case Intrinsic::clmul:
2098 case Intrinsic::pext:
2103 case Intrinsic::pdep:
2108 case Intrinsic::uadd_sat:
2113 case Intrinsic::usub_sat:
2118 case Intrinsic::sadd_sat:
2123 case Intrinsic::ssub_sat:
2129 case Intrinsic::vector_reverse:
2135 case Intrinsic::vector_reduce_and:
2136 case Intrinsic::vector_reduce_or:
2137 case Intrinsic::vector_reduce_umax:
2138 case Intrinsic::vector_reduce_umin:
2139 case Intrinsic::vector_reduce_smax:
2140 case Intrinsic::vector_reduce_smin:
2143 case Intrinsic::vector_reduce_xor: {
2150 bool EvenCnt = VecTy->getElementCount().isKnownEven();
2154 if (VecTy->isScalableTy() || EvenCnt)
2155 Known.One.clearAllBits();
2158 case Intrinsic::vector_reduce_add: {
2163 Known =
Known.reduceAdd(VecTy->getNumElements());
2166 case Intrinsic::umin:
2171 case Intrinsic::umax:
2176 case Intrinsic::smin:
2182 case Intrinsic::smax:
2188 case Intrinsic::ptrmask: {
2191 const Value *Mask =
I->getOperand(1);
2192 Known2 =
KnownBits(Mask->getType()->getScalarSizeInBits());
2198 case Intrinsic::x86_sse2_pmulh_w:
2199 case Intrinsic::x86_avx2_pmulh_w:
2200 case Intrinsic::x86_avx512_pmulh_w_512:
2205 case Intrinsic::x86_sse2_pmulhu_w:
2206 case Intrinsic::x86_avx2_pmulhu_w:
2207 case Intrinsic::x86_avx512_pmulhu_w_512:
2212 case Intrinsic::x86_sse42_crc32_64_64:
2213 Known.Zero.setBitsFrom(32);
2215 case Intrinsic::x86_ssse3_phadd_d_128:
2216 case Intrinsic::x86_ssse3_phadd_w_128:
2217 case Intrinsic::x86_avx2_phadd_d:
2218 case Intrinsic::x86_avx2_phadd_w: {
2220 I, DemandedElts, Q,
Depth,
2226 case Intrinsic::x86_ssse3_phadd_sw_128:
2227 case Intrinsic::x86_avx2_phadd_sw: {
2232 case Intrinsic::x86_ssse3_phsub_d_128:
2233 case Intrinsic::x86_ssse3_phsub_w_128:
2234 case Intrinsic::x86_avx2_phsub_d:
2235 case Intrinsic::x86_avx2_phsub_w: {
2237 I, DemandedElts, Q,
Depth,
2243 case Intrinsic::x86_ssse3_phsub_sw_128:
2244 case Intrinsic::x86_avx2_phsub_sw: {
2249 case Intrinsic::riscv_vsetvli:
2250 case Intrinsic::riscv_vsetvlimax: {
2251 bool HasAVL =
II->getIntrinsicID() == Intrinsic::riscv_vsetvli;
2264 MaxVL = std::min(MaxVL, CI->getZExtValue());
2266 unsigned KnownZeroFirstBit =
Log2_32(MaxVL) + 1;
2268 Known.Zero.setBitsFrom(KnownZeroFirstBit);
2271 case Intrinsic::amdgcn_mbcnt_hi:
2272 case Intrinsic::amdgcn_mbcnt_lo: {
2275 Known.Zero.setBitsFrom(
2276 II->getIntrinsicID() == Intrinsic::amdgcn_mbcnt_lo ? 6 : 5);
2281 case Intrinsic::vscale: {
2282 if (!
II->getParent() || !
II->getFunction())
2288 case Intrinsic::stepvector: {
2290 unsigned MinNumElts = VecTy->getElementCount().getKnownMinValue();
2294 bool Overflow =
false;
2296 if (VecTy->isScalableTy()) {
2297 if (!
II->getParent() || !
II->getFunction())
2301 .
umul_ov(MaxNumElts, Overflow);
2316 case Instruction::ShuffleVector: {
2330 APInt DemandedLHS, DemandedRHS;
2335 Known.setAllConflict();
2336 if (!!DemandedLHS) {
2337 const Value *
LHS = Shuf->getOperand(0);
2340 if (
Known.isUnknown())
2343 if (!!DemandedRHS) {
2344 const Value *
RHS = Shuf->getOperand(1);
2350 case Instruction::InsertElement: {
2355 const Value *Vec =
I->getOperand(0);
2356 const Value *Elt =
I->getOperand(1);
2359 APInt DemandedVecElts = DemandedElts;
2360 bool NeedsElt =
true;
2362 if (CIdx && CIdx->getValue().ult(NumElts)) {
2363 DemandedVecElts.
clearBit(CIdx->getZExtValue());
2364 NeedsElt = DemandedElts[CIdx->getZExtValue()];
2367 Known.setAllConflict();
2371 if (
Known.isUnknown())
2375 if (!DemandedVecElts.
isZero()) {
2381 case Instruction::ExtractElement: {
2384 const Value *Vec =
I->getOperand(0);
2385 const Value *Idx =
I->getOperand(1);
2394 if (CIdx && CIdx->getValue().ult(NumElts))
2399 case Instruction::ExtractValue:
2404 switch (
II->getIntrinsicID()) {
2406 case Intrinsic::uadd_with_overflow:
2407 case Intrinsic::sadd_with_overflow:
2409 true,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2410 false, DemandedElts,
Known, Known2, Q,
Depth);
2412 case Intrinsic::usub_with_overflow:
2413 case Intrinsic::ssub_with_overflow:
2415 false,
II->getArgOperand(0),
II->getArgOperand(1),
false,
2416 false, DemandedElts,
Known, Known2, Q,
Depth);
2418 case Intrinsic::umul_with_overflow:
2419 case Intrinsic::smul_with_overflow:
2421 false, DemandedElts,
Known, Known2, Q,
Depth);
2427 case Instruction::Freeze:
3248 const APInt &DemandedElts,
3251 switch (
I->getOpcode()) {
3252 case Instruction::Alloca:
3254 return I->getType()->getPointerAddressSpace() == 0;
3255 case Instruction::GetElementPtr:
3256 if (
I->getType()->isPointerTy())
3259 case Instruction::BitCast: {
3287 Type *FromTy =
I->getOperand(0)->getType();
3292 case Instruction::IntToPtr:
3301 case Instruction::PtrToAddr:
3305 case Instruction::PtrToInt:
3309 I->getType()->getScalarSizeInBits())
3312 case Instruction::Trunc:
3315 if (TI->hasNoSignedWrap() || TI->hasNoUnsignedWrap())
3321 case Instruction::Xor:
3322 case Instruction::Sub:
3324 I->getOperand(1),
Depth);
3325 case Instruction::Or:
3336 case Instruction::SExt:
3337 case Instruction::ZExt:
3341 case Instruction::Shl: {
3356 case Instruction::LShr:
3357 case Instruction::AShr: {
3367 if (
Known.isNegative())
3387 case Instruction::UDiv:
3388 case Instruction::SDiv: {
3403 if (
I->getOpcode() == Instruction::SDiv) {
3405 XKnown = XKnown.
abs(
false);
3406 YKnown = YKnown.
abs(
false);
3412 return XUgeY && *XUgeY;
3414 case Instruction::Add: {
3424 case Instruction::Mul: {
3430 case Instruction::Select: {
3437 auto SelectArmIsNonZero = [&](
bool IsTrueArm) {
3439 Op = IsTrueArm ?
I->getOperand(1) :
I->getOperand(2);
3457 if (SelectArmIsNonZero(
true) &&
3458 SelectArmIsNonZero(
false))
3462 case Instruction::PHI: {
3473 RecQ.CxtI = PN->getIncomingBlock(U)->getTerminator();
3477 BasicBlock *TrueSucc, *FalseSucc;
3478 if (match(RecQ.CxtI,
3479 m_Br(m_c_ICmp(Pred, m_Specific(U.get()), m_Value(X)),
3480 m_BasicBlock(TrueSucc), m_BasicBlock(FalseSucc)))) {
3482 if ((TrueSucc == PN->getParent()) != (FalseSucc == PN->getParent())) {
3484 if (FalseSucc == PN->getParent())
3485 Pred = CmpInst::getInversePredicate(Pred);
3486 if (cmpExcludesZero(Pred, X))
3494 case Instruction::InsertElement: {
3498 const Value *Vec =
I->getOperand(0);
3499 const Value *Elt =
I->getOperand(1);
3503 APInt DemandedVecElts = DemandedElts;
3504 bool SkipElt =
false;
3506 if (CIdx && CIdx->getValue().ult(NumElts)) {
3507 DemandedVecElts.
clearBit(CIdx->getZExtValue());
3508 SkipElt = !DemandedElts[CIdx->getZExtValue()];
3514 (DemandedVecElts.
isZero() ||
3517 case Instruction::ExtractElement:
3519 const Value *Vec = EEI->getVectorOperand();
3520 const Value *Idx = EEI->getIndexOperand();
3523 unsigned NumElts = VecTy->getNumElements();
3525 if (CIdx && CIdx->getValue().ult(NumElts))
3531 case Instruction::ShuffleVector: {
3535 APInt DemandedLHS, DemandedRHS;
3541 return (DemandedRHS.
isZero() ||
3546 case Instruction::Freeze:
3550 case Instruction::Load: {
3567 case Instruction::ExtractValue: {
3573 case Instruction::Add:
3578 case Instruction::Sub:
3581 case Instruction::Mul:
3584 false,
false,
Depth);
3590 case Instruction::Call:
3591 case Instruction::Invoke: {
3593 if (
I->getType()->isPointerTy()) {
3594 if (
Call->isReturnNonNull())
3602 if (std::optional<ConstantRange>
Range =
Call->getRange()) {
3603 const APInt ZeroValue(
Range->getBitWidth(), 0);
3604 if (!
Range->contains(ZeroValue))
3607 if (
const Value *RV =
Call->getReturnedArgOperand())
3613 switch (
II->getIntrinsicID()) {
3614 case Intrinsic::sshl_sat:
3615 case Intrinsic::ushl_sat:
3616 case Intrinsic::abs:
3617 case Intrinsic::bitreverse:
3618 case Intrinsic::bswap:
3619 case Intrinsic::ctpop:
3623 case Intrinsic::ssub_sat:
3631 case Intrinsic::sadd_sat:
3633 II->getArgOperand(1),
3634 true,
false,
Depth);
3636 case Intrinsic::vector_reverse:
3640 case Intrinsic::vector_reduce_or:
3641 case Intrinsic::vector_reduce_umax:
3642 case Intrinsic::vector_reduce_umin:
3643 case Intrinsic::vector_reduce_smax:
3644 case Intrinsic::vector_reduce_smin:
3646 case Intrinsic::umax:
3647 case Intrinsic::uadd_sat:
3655 case Intrinsic::smax: {
3658 auto IsNonZero = [&](
Value *
Op, std::optional<bool> &OpNonZero,
3660 if (!OpNonZero.has_value())
3661 OpNonZero = OpKnown.isNonZero() ||
3666 std::optional<bool> Op0NonZero, Op1NonZero;
3670 IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known))
3675 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known))
3677 return IsNonZero(
II->getArgOperand(1), Op1NonZero, Op1Known) &&
3678 IsNonZero(
II->getArgOperand(0), Op0NonZero, Op0Known);
3680 case Intrinsic::smin: {
3696 case Intrinsic::umin:
3699 case Intrinsic::cttz:
3702 case Intrinsic::ctlz:
3705 case Intrinsic::fshr:
3706 case Intrinsic::fshl:
3708 if (
II->getArgOperand(0) ==
II->getArgOperand(1))
3711 case Intrinsic::vscale:
3713 case Intrinsic::experimental_get_vector_length:
3727 return Known.One != 0;
4323 const APInt &DemandedElts,
4325 Type *Ty = V->getType();
4331 FVTy->getNumElements() == DemandedElts.
getBitWidth() &&
4332 "DemandedElt width should equal the fixed vector number of elements");
4335 "DemandedElt width should be 1 for scalars");
4349 unsigned FirstAnswer = 1;
4360 case Instruction::BitCast: {
4361 Value *Src = U->getOperand(0);
4362 Type *SrcTy = Src->getType();
4366 if (!SrcTy->isIntOrIntVectorTy())
4372 if ((SrcBits % TyBits) != 0)
4385 case Instruction::SExt:
4386 Tmp = TyBits - U->getOperand(0)->getType()->getScalarSizeInBits();
4390 case Instruction::SDiv: {
4391 const APInt *Denominator;
4404 return std::min(TyBits, NumBits + Denominator->
logBase2());
4409 case Instruction::SRem: {
4412 const APInt *Denominator;
4433 unsigned ResBits = TyBits - Denominator->
ceilLogBase2();
4434 Tmp = std::max(Tmp, ResBits);
4440 case Instruction::AShr: {
4445 if (ShAmt->
uge(TyBits))
4448 Tmp += ShAmtLimited;
4449 if (Tmp > TyBits) Tmp = TyBits;
4453 case Instruction::Shl: {
4458 if (ShAmt->
uge(TyBits))
4463 ShAmt->
uge(TyBits -
X->getType()->getScalarSizeInBits())) {
4465 Tmp += TyBits -
X->getType()->getScalarSizeInBits();
4469 if (ShAmt->
uge(Tmp))
4476 case Instruction::And:
4477 case Instruction::Or:
4478 case Instruction::Xor:
4483 FirstAnswer = std::min(Tmp, Tmp2);
4490 case Instruction::Select: {
4494 const APInt *CLow, *CHigh;
4502 return std::min(Tmp, Tmp2);
4505 case Instruction::Add:
4509 if (Tmp == 1)
break;
4513 if (CRHS->isAllOnesValue()) {
4519 if ((
Known.Zero | 1).isAllOnes())
4524 if (
Known.isNonNegative())
4531 return std::min(Tmp, Tmp2) - 1;
4533 case Instruction::Sub:
4540 if (CLHS->isNullValue()) {
4545 if ((
Known.Zero | 1).isAllOnes())
4551 if (
Known.isNonNegative())
4562 return std::min(Tmp, Tmp2) - 1;
4564 case Instruction::Mul: {
4567 unsigned SignBitsOp0 =
4569 if (SignBitsOp0 == 1)
4571 unsigned SignBitsOp1 =
4573 if (SignBitsOp1 == 1)
4575 unsigned OutValidBits =
4576 (TyBits - SignBitsOp0 + 1) + (TyBits - SignBitsOp1 + 1);
4577 return OutValidBits > TyBits ? 1 : TyBits - OutValidBits + 1;
4580 case Instruction::PHI: {
4584 if (NumIncomingValues > 4)
break;
4586 if (NumIncomingValues == 0)
break;
4592 for (
unsigned i = 0, e = NumIncomingValues; i != e; ++i) {
4593 if (Tmp == 1)
return Tmp;
4596 DemandedElts, RecQ,
Depth + 1));
4601 case Instruction::Trunc: {
4606 unsigned OperandTyBits = U->getOperand(0)->getType()->getScalarSizeInBits();
4607 if (Tmp > (OperandTyBits - TyBits))
4608 return Tmp - (OperandTyBits - TyBits);
4613 case Instruction::ExtractElement:
4620 case Instruction::ShuffleVector: {
4628 APInt DemandedLHS, DemandedRHS;
4633 Tmp = std::numeric_limits<unsigned>::max();
4634 if (!!DemandedLHS) {
4635 const Value *
LHS = Shuf->getOperand(0);
4642 if (!!DemandedRHS) {
4643 const Value *
RHS = Shuf->getOperand(1);
4645 Tmp = std::min(Tmp, Tmp2);
4651 assert(Tmp <= TyBits &&
"Failed to determine minimum sign bits");
4654 case Instruction::Call: {
4656 switch (
II->getIntrinsicID()) {
4659 case Intrinsic::abs:
4667 case Intrinsic::smin:
4668 case Intrinsic::smax: {
4669 const APInt *CLow, *CHigh;
4684 if (
unsigned VecSignBits =
4693 return std::max(FirstAnswer,
Known.countMinSignBits());
5124 assert(
Known.isUnknown() &&
"should not be called with known information");
5126 if (!DemandedElts) {
5141 Known.SignBit =
false;
5147 Known.SignBit =
false;
5156 bool SignBitAllZero =
true;
5157 bool SignBitAllOne =
true;
5160 unsigned NumElts = VFVTy->getNumElements();
5161 for (
unsigned i = 0; i != NumElts; ++i) {
5162 if (!DemandedElts[i])
5178 const APFloat &
C = CElt->getValueAPF();
5179 Known.KnownFPClasses |=
C.classify();
5181 SignBitAllZero =
false;
5183 SignBitAllOne =
false;
5185 if (SignBitAllOne != SignBitAllZero)
5186 Known.SignBit = SignBitAllOne;
5192 for (
size_t I = 0,
E = CDS->getNumElements();
I !=
E; ++
I)
5193 Known |= CDS->getElementAsAPFloat(
I).classify();
5200 for (
const Use &
Op : CA->operands()) {
5207 Known |= CFP->getValueAPF().classify();
5215 KnownNotFromFlags |= CB->getRetNoFPClass();
5217 KnownNotFromFlags |= Arg->getNoFPClass();
5221 if (FPOp->hasNoNaNs())
5222 KnownNotFromFlags |=
fcNan;
5223 if (FPOp->hasNoInfs())
5224 KnownNotFromFlags |=
fcInf;
5228 KnownNotFromFlags |= ~AssumedClasses.KnownFPClasses;
5232 InterestedClasses &= ~KnownNotFromFlags;
5235 Known.knownNot(KnownNotFromFlags);
5238 Known.signBitMustBeOne();
5240 Known.signBitMustBeZero();
5251 const unsigned Opc =
Op->getOpcode();
5253 case Instruction::FNeg: {
5259 case Instruction::Select: {
5260 auto ComputeForArm = [&](
Value *Arm,
bool Invert) {
5270 ComputeForArm(
Op->getOperand(1),
false)
5271 .intersectWith(ComputeForArm(
Op->getOperand(2),
true));
5274 case Instruction::Load: {
5275 const MDNode *NoFPClass =
5285 case Instruction::Call: {
5289 case Intrinsic::fabs: {
5300 case Intrinsic::copysign: {
5306 KnownSign, Q,
Depth + 1);
5307 Known.copysign(KnownSign);
5310 case Intrinsic::fma:
5311 case Intrinsic::fmuladd: {
5316 if (
II->getArgOperand(0) ==
II->getArgOperand(1)) {
5319 InterestedClasses, KnownAddend, Q,
Depth + 1);
5321 InterestedClasses, KnownSrc, Q,
Depth + 1);
5325 II->getType()->getScalarType()->getFltSemantics();
5329 if (KnownNotFromFlags &
fcNan) {
5334 if (KnownNotFromFlags &
fcInf) {
5344 for (
int I = 0;
I != 3; ++
I) {
5346 InterestedClasses, KnownSrc[
I], Q,
Depth + 1);
5347 if (KnownSrc[
I].isUnknown())
5350 if (KnownNotFromFlags &
fcNan)
5352 if (KnownNotFromFlags &
fcInf)
5358 II->getType()->getScalarType()->getFltSemantics();
5364 case Intrinsic::sqrt:
5365 case Intrinsic::experimental_constrained_sqrt: {
5368 if (InterestedClasses &
fcNan)
5372 KnownSrc, Q,
Depth + 1);
5380 II->getType()->getScalarType()->getFltSemantics();
5390 case Intrinsic::sin: {
5393 KnownSrc, Q,
Depth + 1);
5397 case Intrinsic::cos: {
5400 KnownSrc, Q,
Depth + 1);
5404 case Intrinsic::tan: {
5407 KnownSrc, Q,
Depth + 1);
5411 case Intrinsic::sinh: {
5414 KnownSrc, Q,
Depth + 1);
5418 case Intrinsic::cosh: {
5421 KnownSrc, Q,
Depth + 1);
5425 case Intrinsic::tanh: {
5428 KnownSrc, Q,
Depth + 1);
5432 case Intrinsic::asin: {
5435 KnownSrc, Q,
Depth + 1);
5439 case Intrinsic::acos: {
5442 KnownSrc, Q,
Depth + 1);
5446 case Intrinsic::atan: {
5449 KnownSrc, Q,
Depth + 1);
5453 case Intrinsic::atan2: {
5463 KnownY, Q,
Depth + 1);
5465 KnownX, Q,
Depth + 1);
5469 F ?
F->getDenormalMode(
5470 II->getType()->getScalarType()->getFltSemantics())
5475 case Intrinsic::maxnum:
5476 case Intrinsic::minnum:
5477 case Intrinsic::minimum:
5478 case Intrinsic::maximum:
5479 case Intrinsic::minimumnum:
5480 case Intrinsic::maximumnum: {
5483 KnownLHS, Q,
Depth + 1);
5485 KnownRHS, Q,
Depth + 1);
5490 F ?
F->getDenormalMode(
5491 II->getType()->getScalarType()->getFltSemantics())
5498 case Intrinsic::canonicalize: {
5501 KnownSrc, Q,
Depth + 1);
5505 F ?
F->getDenormalMode(
5506 II->getType()->getScalarType()->getFltSemantics())
5511 case Intrinsic::vector_reduce_fmax:
5512 case Intrinsic::vector_reduce_fmin:
5513 case Intrinsic::vector_reduce_fmaximum:
5514 case Intrinsic::vector_reduce_fminimum:
5515 case Intrinsic::vector_reduce_fmaximumnum:
5516 case Intrinsic::vector_reduce_fminimumnum: {
5520 InterestedClasses, Q,
Depth + 1);
5522 if (!
Known.isKnownNeverNaN())
5523 Known.SignBit.reset();
5527 case Intrinsic::vector_reverse:
5530 II->getFastMathFlags(), InterestedClasses, Q,
Depth + 1);
5532 case Intrinsic::trunc:
5533 case Intrinsic::floor:
5534 case Intrinsic::ceil:
5535 case Intrinsic::rint:
5536 case Intrinsic::nearbyint:
5537 case Intrinsic::round:
5538 case Intrinsic::roundeven: {
5546 KnownSrc, Q,
Depth + 1);
5549 KnownSrc, IID == Intrinsic::trunc,
5550 V->getType()->getScalarType()->isMultiUnitFPType());
5553 case Intrinsic::exp:
5554 case Intrinsic::exp2:
5555 case Intrinsic::exp10:
5556 case Intrinsic::amdgcn_exp2: {
5559 KnownSrc, Q,
Depth + 1);
5563 Type *EltTy =
II->getType()->getScalarType();
5564 if (IID == Intrinsic::amdgcn_exp2 && EltTy->
isFloatTy())
5569 case Intrinsic::fptrunc_round: {
5574 case Intrinsic::log:
5575 case Intrinsic::log10:
5576 case Intrinsic::log2:
5577 case Intrinsic::experimental_constrained_log:
5578 case Intrinsic::experimental_constrained_log10:
5579 case Intrinsic::experimental_constrained_log2:
5580 case Intrinsic::amdgcn_log: {
5581 Type *EltTy =
II->getType()->getScalarType();
5596 KnownSrc, Q,
Depth + 1);
5606 case Intrinsic::pow: {
5607 const bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5609 if (!WantNaN && !WantNegative)
5619 InterestedRHS |=
fcNan;
5630 KnownLHS, Q,
Depth + 1);
5639 KnownRHS, Q,
Depth + 1);
5643 case Intrinsic::powi: {
5648 const Value *Exp =
II->getArgOperand(1);
5649 unsigned BitWidth = Exp->getType()->getIntegerBitWidth();
5654 if (InterestedClasses &
fcNan)
5655 InterestedSrcs |=
fcNan;
5656 if (!ExponentKnownBits.
isZero()) {
5657 if (InterestedClasses &
fcInf)
5664 if (InterestedSrcs !=
fcNone)
5666 KnownSrc, Q,
Depth + 1);
5671 case Intrinsic::ldexp: {
5674 KnownSrc, Q,
Depth + 1);
5678 const Value *ExpArg =
II->getArgOperand(1);
5682 : ConstantRange::getFull(
5686 II->getType()->getScalarType()->getFltSemantics();
5696 case Intrinsic::arithmetic_fence: {
5701 case Intrinsic::experimental_constrained_sitofp:
5702 case Intrinsic::experimental_constrained_uitofp:
5712 if (IID == Intrinsic::experimental_constrained_uitofp)
5713 Known.signBitMustBeZero();
5718 case Intrinsic::amdgcn_fract: {
5721 if (InterestedClasses &
fcNan) {
5724 InterestedClasses, KnownSrc, Q,
Depth + 1);
5734 case Intrinsic::amdgcn_rcp: {
5737 KnownSrc, Q,
Depth + 1);
5739 Known.propagateNonNaN(KnownSrc);
5741 Type *EltTy =
II->getType()->getScalarType();
5764 case Intrinsic::amdgcn_rsq: {
5770 KnownSrc, Q,
Depth + 1);
5782 Type *EltTy =
II->getType()->getScalarType();
5802 case Intrinsic::amdgcn_trig_preop: {
5807 case Intrinsic::convert_from_arbitrary_fp: {
5817 II->getType()->getScalarType()->getFltSemantics();
5852 case Instruction::FAdd:
5853 case Instruction::FSub: {
5856 Op->getOpcode() == Instruction::FAdd &&
5858 bool WantNaN = (InterestedClasses &
fcNan) !=
fcNone;
5861 if (!WantNaN && !WantNegative && !WantNegZero)
5867 if (InterestedClasses &
fcNan)
5868 InterestedSrcs |=
fcInf;
5870 KnownRHS, Q,
Depth + 1);
5873 bool Self =
Op->getOperand(0) ==
Op->getOperand(1) &&
5877 KnownLHS = KnownRHS;
5881 WantNegZero ||
Opc == Instruction::FSub) {
5886 Op->getType()->getScalarType()->getFltSemantics();
5890 if (Self &&
Opc == Instruction::FAdd) {
5898 KnownLHS, Q,
Depth + 1);
5909 case Instruction::FMul: {
5912 F ?
F->getDenormalMode(
5913 Op->getType()->getScalarType()->getFltSemantics())
5956 case Instruction::FDiv: {
5957 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
5961 Op->getType()->getScalarType()->getFltSemantics();
5965 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
5984 if (!WantNan && !WantNegative && !WantPositive)
5991 bool KnowSomethingUseful =
5996 if (KnowSomethingUseful)
6003 case Instruction::FRem: {
6004 const bool WantNan = (InterestedClasses &
fcNan) !=
fcNone;
6010 F ?
F->getDenormalMode(
6011 Op->getType()->getScalarType()->getFltSemantics())
6014 if (
Op->getOperand(0) ==
Op->getOperand(1) &&
6033 if (!WantNan && !WantNegative && !WantPositive)
6045 if (KnowSomethingUseful || WantPositive)
6053 case Instruction::FPExt: {
6056 KnownSrc, Q,
Depth + 1);
6059 Op->getType()->getScalarType()->getFltSemantics();
6061 Op->getOperand(0)->getType()->getScalarType()->getFltSemantics();
6066 case Instruction::FPTrunc: {
6071 case Instruction::SIToFP:
6072 case Instruction::UIToFP: {
6083 if (
Op->getOpcode() == Instruction::UIToFP)
6084 Known.signBitMustBeZero();
6097 if (
Op->getOpcode() == Instruction::SIToFP) {
6102 Known.signBitMustBeZero();
6104 Known.signBitMustBeOne();
6109 if (InterestedClasses &
fcInf) {
6114 if (
Op->getOpcode() == Instruction::UIToFP)
6116 else if (
Op->getOpcode() == Instruction::SIToFP)
6121 Type *FPTy =
Op->getType()->getScalarType();
6128 case Instruction::ExtractElement: {
6131 const Value *Vec =
Op->getOperand(0);
6133 APInt DemandedVecElts;
6135 unsigned NumElts = VecTy->getNumElements();
6138 if (CIdx && CIdx->getValue().ult(NumElts))
6141 DemandedVecElts =
APInt(1, 1);
6147 case Instruction::InsertElement: {
6151 const Value *Vec =
Op->getOperand(0);
6152 const Value *Elt =
Op->getOperand(1);
6155 APInt DemandedVecElts = DemandedElts;
6156 bool NeedsElt =
true;
6158 if (CIdx && CIdx->getValue().ult(NumElts)) {
6159 DemandedVecElts.
clearBit(CIdx->getZExtValue());
6160 NeedsElt = DemandedElts[CIdx->getZExtValue()];
6167 if (
Known.isUnknown())
6174 if (!DemandedVecElts.
isZero()) {
6183 case Instruction::ShuffleVector: {
6192 APInt DemandedLHS, DemandedRHS;
6197 if (!!DemandedLHS) {
6198 const Value *
LHS = Shuf->getOperand(0);
6203 if (
Known.isUnknown())
6209 if (!!DemandedRHS) {
6211 const Value *
RHS = Shuf->getOperand(1);
6219 case Instruction::ExtractValue: {
6226 switch (
II->getIntrinsicID()) {
6227 case Intrinsic::frexp: {
6232 InterestedClasses, KnownSrc, Q,
Depth + 1);
6236 Op->getType()->getScalarType()->getFltSemantics();
6253 case Instruction::PHI: {
6256 if (
P->getNumIncomingValues() == 0)
6263 if (
Depth < PhiRecursionLimit) {
6270 for (
const Use &U :
P->operands()) {
6301 if (
P->getNumIncomingValues() != 2 ||
Known.cannotBeOrderedLessThanZero())
6303 for (
unsigned I = 0;
I < 2;
I++) {
6304 Value *RecurValue =
P->getIncomingValue(1 -
I);
6312 switch (
II->getIntrinsicID()) {
6313 case Intrinsic::fma:
6314 case Intrinsic::fmuladd: {
6328 case Instruction::BitCast: {
6331 !Src->getType()->isIntOrIntVectorTy())
6334 const Type *Ty =
Op->getType();
6336 Value *CastLHS, *CastRHS;
6348 Known = KnownLHS | KnownRHS;