Merged
7 tasks
ThomasRaoux pushed a commit that referenced this pull request
Mar 3, 2026These tests weren't checking anything and would pass even after swapping the correct call_intrinsic to XXX_BROKEN, noticed this while working on #9628 <!--- The core Triton is a small number of people, and we receive many PRs (thank you!). To help us review your code more quickly, **if you are a new contributor (less than 3 PRs merged) we ask that you complete the following tasks and include the filled-out checklist in your PR description.** Complete the following tasks before sending your PR, and replace `[ ]` with `[x]` to indicate you have done them. --> # New contributor declaration - [x] I am not making a trivial change, such as fixing a typo in a comment. - [x] I have written a PR description following these [rules](https://cbea.ms/git-commit/#why-not-how). - [x] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`. - Select one of the following. - [ ] I have added tests. - `/test` for `lit` tests - `/unittest` for C++ tests - `/python/test` for end-to-end tests - [x] This PR does not need a test because `Fixing existing tests`. - Select one of the following. - [x] I have not added any `lit` tests. - [ ] The `lit` tests I have added follow these [best practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices), including the "tests should be minimal" section. (Usually running Python code and using the instructions it generates is not minimal.)
gfx906 previously mapped to ISAFamily::Unknown, which
caused a hard failure in TritonGPUToLLVM and ConvertWarpPipeline
("unsupported target"). gfx906 has v_dot2_f32_f16 and v_dot4_i32_i8
via VOP3P but no MFMA — same dot intrinsics as gfx908, just without
the compact VOP2 encoding. LLVM handles this transparently via
HasDot1Insts/HasDot2Insts feature bits.
The warpReduce check previously used negative enumeration (exclude
CDNA1, exclude RDNA1/2) to gate DPP warp reduction. Adding gfx906
would have required yet another exclusion. Replaced with an
IsaVersion-based gfx90a+ or gfx11+ gate to future-proof.
gfx906 is on AMD's official prioritized architecture support
roadmap.
ISA Roadmap: https://github.com/ROCm/TheRock/blob/b1ebfea/ROADMAP.md
gfx906 insns: https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX906.html
gfx908 insns: https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX908.html
LunNova
changed the title
[AMD] Add gfx906 (Radeon VII / MI50 / MI60) target
[AMD] Add GCN5.1 (gfx906: Radeon VII / MI50 / MI60) target
LunNova marked this pull request as ready for review
March 6, 2026 15:09
antiagainst
changed the title
[AMD] Add GCN5.1 (gfx906: Radeon VII / MI50 / MI60) target
[AMD] Add GCN5.1 / gfx906 target
Merged
13 tasks
Closed
raymondtay pushed a commit to raymondtay/triton that referenced this pull request
Mar 22, 2026) These tests weren't checking anything and would pass even after swapping the correct call_intrinsic to XXX_BROKEN, noticed this while working on triton-lang#9628 <!--- The core Triton is a small number of people, and we receive many PRs (thank you!). To help us review your code more quickly, **if you are a new contributor (less than 3 PRs merged) we ask that you complete the following tasks and include the filled-out checklist in your PR description.** Complete the following tasks before sending your PR, and replace `[ ]` with `[x]` to indicate you have done them. --> # New contributor declaration - [x] I am not making a trivial change, such as fixing a typo in a comment. - [x] I have written a PR description following these [rules](https://cbea.ms/git-commit/#why-not-how). - [x] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`. - Select one of the following. - [ ] I have added tests. - `/test` for `lit` tests - `/unittest` for C++ tests - `/python/test` for end-to-end tests - [x] This PR does not need a test because `Fixing existing tests`. - Select one of the following. - [x] I have not added any `lit` tests. - [ ] The `lit` tests I have added follow these [best practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices), including the "tests should be minimal" section. (Usually running Python code and using the instructions it generates is not minimal.)
raymondtay pushed a commit to raymondtay/triton that referenced this pull request
Mar 22, 2026[gfx906 has](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX906.html) v_dot2_f32_f16 and v_dot4_i32_i8 via VOP3P but no MFMA. Nearly the same dot intrinsics as [gfx908](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX908.html); LLVM transparently selects correct form based on HasDot1Insts/HasDot2Insts feature bits. New ISAFamily::GCN5_1 enum mapped from GK_GFX906 with wave64, DPP broadcast, and supportsVDot; this is GCN so not marked as RDNA/CDNA and most gates don't need updated. warpReduce refactored from isCDNA/isRDNA negative enumeration to a `getIsaVersion()` check (gfx90a+ || gfx11+).
jvican pushed a commit to jvican/triton that referenced this pull request
Mar 27, 2026) These tests weren't checking anything and would pass even after swapping the correct call_intrinsic to XXX_BROKEN, noticed this while working on triton-lang#9628 <!--- The core Triton is a small number of people, and we receive many PRs (thank you!). To help us review your code more quickly, **if you are a new contributor (less than 3 PRs merged) we ask that you complete the following tasks and include the filled-out checklist in your PR description.** Complete the following tasks before sending your PR, and replace `[ ]` with `[x]` to indicate you have done them. --> # New contributor declaration - [x] I am not making a trivial change, such as fixing a typo in a comment. - [x] I have written a PR description following these [rules](https://cbea.ms/git-commit/#why-not-how). - [x] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`. - Select one of the following. - [ ] I have added tests. - `/test` for `lit` tests - `/unittest` for C++ tests - `/python/test` for end-to-end tests - [x] This PR does not need a test because `Fixing existing tests`. - Select one of the following. - [x] I have not added any `lit` tests. - [ ] The `lit` tests I have added follow these [best practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices), including the "tests should be minimal" section. (Usually running Python code and using the instructions it generates is not minimal.)
jvican pushed a commit to jvican/triton that referenced this pull request
Mar 27, 2026[gfx906 has](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX906.html) v_dot2_f32_f16 and v_dot4_i32_i8 via VOP3P but no MFMA. Nearly the same dot intrinsics as [gfx908](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX908.html); LLVM transparently selects correct form based on HasDot1Insts/HasDot2Insts feature bits. New ISAFamily::GCN5_1 enum mapped from GK_GFX906 with wave64, DPP broadcast, and supportsVDot; this is GCN so not marked as RDNA/CDNA and most gates don't need updated. warpReduce refactored from isCDNA/isRDNA negative enumeration to a `getIsaVersion()` check (gfx90a+ || gfx11+).
plognjen pushed a commit to plognjen/triton that referenced this pull request
Apr 14, 2026) These tests weren't checking anything and would pass even after swapping the correct call_intrinsic to XXX_BROKEN, noticed this while working on triton-lang#9628 <!--- The core Triton is a small number of people, and we receive many PRs (thank you!). To help us review your code more quickly, **if you are a new contributor (less than 3 PRs merged) we ask that you complete the following tasks and include the filled-out checklist in your PR description.** Complete the following tasks before sending your PR, and replace `[ ]` with `[x]` to indicate you have done them. --> # New contributor declaration - [x] I am not making a trivial change, such as fixing a typo in a comment. - [x] I have written a PR description following these [rules](https://cbea.ms/git-commit/#why-not-how). - [x] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`. - Select one of the following. - [ ] I have added tests. - `/test` for `lit` tests - `/unittest` for C++ tests - `/python/test` for end-to-end tests - [x] This PR does not need a test because `Fixing existing tests`. - Select one of the following. - [x] I have not added any `lit` tests. - [ ] The `lit` tests I have added follow these [best practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices), including the "tests should be minimal" section. (Usually running Python code and using the instructions it generates is not minimal.)
plognjen pushed a commit to plognjen/triton that referenced this pull request
Apr 14, 2026[gfx906 has](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX906.html) v_dot2_f32_f16 and v_dot4_i32_i8 via VOP3P but no MFMA. Nearly the same dot intrinsics as [gfx908](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX908.html); LLVM transparently selects correct form based on HasDot1Insts/HasDot2Insts feature bits. New ISAFamily::GCN5_1 enum mapped from GK_GFX906 with wave64, DPP broadcast, and supportsVDot; this is GCN so not marked as RDNA/CDNA and most gates don't need updated. warpReduce refactored from isCDNA/isRDNA negative enumeration to a `getIsaVersion()` check (gfx90a+ || gfx11+).
ngocson2vn pushed a commit to ngocson2vn/triton that referenced this pull request
Jul 5, 2026) These tests weren't checking anything and would pass even after swapping the correct call_intrinsic to XXX_BROKEN, noticed this while working on triton-lang#9628 <!--- The core Triton is a small number of people, and we receive many PRs (thank you!). To help us review your code more quickly, **if you are a new contributor (less than 3 PRs merged) we ask that you complete the following tasks and include the filled-out checklist in your PR description.** Complete the following tasks before sending your PR, and replace `[ ]` with `[x]` to indicate you have done them. --> # New contributor declaration - [x] I am not making a trivial change, such as fixing a typo in a comment. - [x] I have written a PR description following these [rules](https://cbea.ms/git-commit/#why-not-how). - [x] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`. - Select one of the following. - [ ] I have added tests. - `/test` for `lit` tests - `/unittest` for C++ tests - `/python/test` for end-to-end tests - [x] This PR does not need a test because `Fixing existing tests`. - Select one of the following. - [x] I have not added any `lit` tests. - [ ] The `lit` tests I have added follow these [best practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices), including the "tests should be minimal" section. (Usually running Python code and using the instructions it generates is not minimal.)
ngocson2vn pushed a commit to ngocson2vn/triton that referenced this pull request
Jul 5, 2026[gfx906 has](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX906.html) v_dot2_f32_f16 and v_dot4_i32_i8 via VOP3P but no MFMA. Nearly the same dot intrinsics as [gfx908](https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX908.html); LLVM transparently selects correct form based on HasDot1Insts/HasDot2Insts feature bits. New ISAFamily::GCN5_1 enum mapped from GK_GFX906 with wave64, DPP broadcast, and supportsVDot; this is GCN so not marked as RDNA/CDNA and most gates don't need updated. warpReduce refactored from isCDNA/isRDNA negative enumeration to a `getIsaVersion()` check (gfx90a+ || gfx11+).