added reset output to use when the axi_stream_master is generating the reset.
changed wait until idle construction to use a notify from the bus process so that we are sure all transactions (including the reset) have been handled.
added checking of reset input on places where it is required so that a reset is handled properly in the master.
added axi_stream_reset to vci.
added reset input to axi_stream_slave.vhd.
added basic test for reset functionality.

replaced reset out / reset in, with single reset input.
adapted testbench.