allins.hpp

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/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
NN_null = 0,            // Unknown Operation
NN_aaa,                 // ASCII Adjust after Addition
NN_aad,                 // ASCII Adjust AX before Division
NN_aam,                 // ASCII Adjust AX after Multiply
NN_aas,                 // ASCII Adjust AL after Subtraction
NN_adc,                 // Add with Carry
NN_add,                 // Add
NN_and,                 // Logical AND
NN_arpl,                // Adjust RPL Field of Selector
NN_bound,               // Check Array Index Against Bounds
NN_bsf,                 // Bit Scan Forward
NN_bsr,                 // Bit Scan Reverse
NN_bt,                  // Bit Test
NN_btc,                 // Bit Test and Complement
NN_btr,                 // Bit Test and Reset
NN_bts,                 // Bit Test and Set
NN_call,                // Call Procedure
NN_callfi,              // Indirect Call Far Procedure
NN_callni,              // Indirect Call Near Procedure
NN_cbw,                 // AL -> AX (with sign)
NN_cwde,                // AX -> EAX (with sign)
NN_cdqe,                // EAX -> RAX (with sign)
NN_clc,                 // Clear Carry Flag
NN_cld,                 // Clear Direction Flag
NN_cli,                 // Clear Interrupt Flag
NN_clts,                // Clear Task-Switched Flag in CR0
NN_cmc,                 // Complement Carry Flag
NN_cmp,                 // Compare Two Operands
NN_cmps,                // Compare Strings
NN_cwd,                 // AX -> DX:AX (with sign)
NN_cdq,                 // EAX -> EDX:EAX (with sign)
NN_cqo,                 // RAX -> RDX:RAX (with sign)
NN_daa,                 // Decimal Adjust AL after Addition
NN_das,                 // Decimal Adjust AL after Subtraction
NN_dec,                 // Decrement by 1
NN_div,                 // Unsigned Divide
NN_enterw,              // Make Stack Frame for Procedure Parameters
NN_enter,               // Make Stack Frame for Procedure Parameters
NN_enterd,              // Make Stack Frame for Procedure Parameters
NN_enterq,              // Make Stack Frame for Procedure Parameters
NN_hlt,                 // Halt
NN_idiv,                // Signed Divide
NN_imul,                // Signed Multiply
NN_in,                  // Input from Port
NN_inc,                 // Increment by 1
NN_ins,                 // Input Byte(s) from Port to String
NN_int,                 // Call to Interrupt Procedure
NN_into,                // Call to Interrupt Procedure if Overflow Flag = 1
NN_int3,                // Trap to Debugger
NN_iretw,               // Interrupt Return
NN_iret,                // Interrupt Return
NN_iretd,               // Interrupt Return (use32)
NN_iretq,               // Interrupt Return (use64)
NN_ja,                  // Jump if Above (CF=0 & ZF=0)
NN_jae,                 // Jump if Above or Equal (CF=0)
NN_jb,                  // Jump if Below (CF=1)
NN_jbe,                 // Jump if Below or Equal (CF=1 | ZF=1)
NN_jc,                  // Jump if Carry (CF=1)
NN_jcxz,                // Jump if CX is 0
NN_jecxz,               // Jump if ECX is 0
NN_jrcxz,               // Jump if RCX is 0
NN_je,                  // Jump if Equal (ZF=1)
NN_jg,                  // Jump if Greater (ZF=0 & SF=OF)
NN_jge,                 // Jump if Greater or Equal (SF=OF)
NN_jl,                  // Jump if Less (SF!=OF)
NN_jle,                 // Jump if Less or Equal (ZF=1 | SF!=OF)
NN_jna,                 // Jump if Not Above (CF=1 | ZF=1)
NN_jnae,                // Jump if Not Above or Equal (CF=1)
NN_jnb,                 // Jump if Not Below (CF=0)
NN_jnbe,                // Jump if Not Below or Equal (CF=0 & ZF=0)
NN_jnc,                 // Jump if Not Carry (CF=0)
NN_jne,                 // Jump if Not Equal (ZF=0)
NN_jng,                 // Jump if Not Greater (ZF=1 | SF!=OF)
NN_jnge,                // Jump if Not Greater or Equal (ZF=1)
NN_jnl,                 // Jump if Not Less (SF=OF)
NN_jnle,                // Jump if Not Less or Equal (ZF=0 & SF=OF)
NN_jno,                 // Jump if Not Overflow (OF=0)
NN_jnp,                 // Jump if Not Parity (PF=0)
NN_jns,                 // Jump if Not Sign (SF=0)
NN_jnz,                 // Jump if Not Zero (ZF=0)
NN_jo,                  // Jump if Overflow (OF=1)
NN_jp,                  // Jump if Parity (PF=1)
NN_jpe,                 // Jump if Parity Even (PF=1)
NN_jpo,                 // Jump if Parity Odd  (PF=0)
NN_js,                  // Jump if Sign (SF=1)
NN_jz,                  // Jump if Zero (ZF=1)
NN_jmp,                 // Jump
NN_jmpfi,               // Indirect Far Jump
NN_jmpni,               // Indirect Near Jump
NN_jmpshort,            // Jump Short (not used)
NN_lahf,                // Load Flags into AH Register
NN_lar,                 // Load Access Right Byte
NN_lea,                 // Load Effective Address
NN_leavew,              // High Level Procedure Exit
NN_leave,               // High Level Procedure Exit
NN_leaved,              // High Level Procedure Exit
NN_leaveq,              // High Level Procedure Exit
NN_lgdt,                // Load Global Descriptor Table Register
NN_lidt,                // Load Interrupt Descriptor Table Register
NN_lgs,                 // Load Full Pointer to GS:xx
NN_lss,                 // Load Full Pointer to SS:xx
NN_lds,                 // Load Full Pointer to DS:xx
NN_les,                 // Load Full Pointer to ES:xx
NN_lfs,                 // Load Full Pointer to FS:xx
NN_lldt,                // Load Local Descriptor Table Register
NN_lmsw,                // Load Machine Status Word
NN_lock,                // Assert LOCK# Signal Prefix
NN_lods,                // Load String
NN_loopw,               // Loop while ECX != 0
NN_loop,                // Loop while CX != 0
NN_loopd,               // Loop while ECX != 0
NN_loopq,               // Loop while RCX != 0
NN_loopwe,              // Loop while CX != 0 and ZF=1
NN_loope,               // Loop while rCX != 0 and ZF=1
NN_loopde,              // Loop while ECX != 0 and ZF=1
NN_loopqe,              // Loop while RCX != 0 and ZF=1
NN_loopwne,             // Loop while CX != 0 and ZF=0
NN_loopne,              // Loop while rCX != 0 and ZF=0
NN_loopdne,             // Loop while ECX != 0 and ZF=0
NN_loopqne,             // Loop while RCX != 0 and ZF=0
NN_lsl,                 // Load Segment Limit
NN_ltr,                 // Load Task Register
NN_mov,                 // Move Data
NN_movsp,               // Move to/from Special Registers
NN_movs,                // Move Byte(s) from String to String
NN_movsx,               // Move with Sign-Extend
NN_movzx,               // Move with Zero-Extend
NN_mul,                 // Unsigned Multiplication of AL or AX
NN_neg,                 // Two's Complement Negation
NN_nop,                 // No Operation
NN_not,                 // One's Complement Negation
NN_or,                  // Logical Inclusive OR
NN_out,                 // Output to Port
NN_outs,                // Output Byte(s) to Port
NN_pop,                 // Pop a word from the Stack
NN_popaw,               // Pop all General Registers
NN_popa,                // Pop all General Registers
NN_popad,               // Pop all General Registers (use32)
NN_popaq,               // Pop all General Registers (use64)
NN_popfw,               // Pop Stack into Flags Register
NN_popf,                // Pop Stack into Flags Register
NN_popfd,               // Pop Stack into Eflags Register
NN_popfq,               // Pop Stack into Rflags Register
NN_push,                // Push Operand onto the Stack
NN_pushaw,              // Push all General Registers
NN_pusha,               // Push all General Registers
NN_pushad,              // Push all General Registers (use32)
NN_pushaq,              // Push all General Registers (use64)
NN_pushfw,              // Push Flags Register onto the Stack
NN_pushf,               // Push Flags Register onto the Stack
NN_pushfd,              // Push Flags Register onto the Stack (use32)
NN_pushfq,              // Push Flags Register onto the Stack (use64)
NN_rcl,                 // Rotate Through Carry Left
NN_rcr,                 // Rotate Through Carry Right
NN_rol,                 // Rotate Left
NN_ror,                 // Rotate Right
NN_rep,                 // Repeat String Operation
NN_repe,                // Repeat String Operation while ZF=1
NN_repne,               // Repeat String Operation while ZF=0
NN_retn,                // Return Near from Procedure
NN_retf,                // Return Far from Procedure
NN_sahf,                // Store AH into Flags Register
NN_sal,                 // Shift Arithmetic Left
NN_sar,                 // Shift Arithmetic Right
NN_shl,                 // Shift Logical Left
NN_shr,                 // Shift Logical Right
NN_sbb,                 // Integer Subtraction with Borrow
NN_scas,                // Compare String
NN_seta,                // Set Byte if Above (CF=0 & ZF=0)
NN_setae,               // Set Byte if Above or Equal (CF=0)
NN_setb,                // Set Byte if Below (CF=1)
NN_setbe,               // Set Byte if Below or Equal (CF=1 | ZF=1)
NN_setc,                // Set Byte if Carry (CF=1)
NN_sete,                // Set Byte if Equal (ZF=1)
NN_setg,                // Set Byte if Greater (ZF=0 & SF=OF)
NN_setge,               // Set Byte if Greater or Equal (SF=OF)
NN_setl,                // Set Byte if Less (SF!=OF)
NN_setle,               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
NN_setna,               // Set Byte if Not Above (CF=1 | ZF=1)
NN_setnae,              // Set Byte if Not Above or Equal (CF=1)
NN_setnb,               // Set Byte if Not Below (CF=0)
NN_setnbe,              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
NN_setnc,               // Set Byte if Not Carry (CF=0)
NN_setne,               // Set Byte if Not Equal (ZF=0)
NN_setng,               // Set Byte if Not Greater (ZF=1 | SF!=OF)
NN_setnge,              // Set Byte if Not Greater or Equal (ZF=1)
NN_setnl,               // Set Byte if Not Less (SF=OF)
NN_setnle,              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
NN_setno,               // Set Byte if Not Overflow (OF=0)
NN_setnp,               // Set Byte if Not Parity (PF=0)
NN_setns,               // Set Byte if Not Sign (SF=0)
NN_setnz,               // Set Byte if Not Zero (ZF=0)
NN_seto,                // Set Byte if Overflow (OF=1)
NN_setp,                // Set Byte if Parity (PF=1)
NN_setpe,               // Set Byte if Parity Even (PF=1)
NN_setpo,               // Set Byte if Parity Odd  (PF=0)
NN_sets,                // Set Byte if Sign (SF=1)
NN_setz,                // Set Byte if Zero (ZF=1)
NN_sgdt,                // Store Global Descriptor Table Register
NN_sidt,                // Store Interrupt Descriptor Table Register
NN_shld,                // Double Precision Shift Left
NN_shrd,                // Double Precision Shift Right
NN_sldt,                // Store Local Descriptor Table Register
NN_smsw,                // Store Machine Status Word
NN_stc,                 // Set Carry Flag
NN_std,                 // Set Direction Flag
NN_sti,                 // Set Interrupt Flag
NN_stos,                // Store String
NN_str,                 // Store Task Register
NN_sub,                 // Integer Subtraction
NN_test,                // Logical Compare
NN_verr,                // Verify a Segment for Reading
NN_verw,                // Verify a Segment for Writing
NN_wait,                // Wait until BUSY# Pin is Inactive (HIGH)
NN_xchg,                // Exchange Register/Memory with Register
NN_xlat,                // Table Lookup Translation
NN_xor,                 // Logical Exclusive OR
//
//      486 instructions
//
NN_cmpxchg,             // Compare and Exchange
NN_bswap,               // Swap bits in EAX
NN_xadd,                // t<-dest; dest<-src+dest; src<-t
NN_invd,                // Invalidate Data Cache
NN_wbinvd,              // Invalidate Data Cache (write changes)
NN_invlpg,              // Invalidate TLB entry
//
//      Pentium instructions
//
NN_rdmsr,               // Read Machine Status Register
NN_wrmsr,               // Write Machine Status Register
NN_cpuid,               // Get CPU ID
NN_cmpxchg8b,           // Compare and Exchange Eight Bytes
NN_rdtsc,               // Read Time Stamp Counter
NN_rsm,                 // Resume from System Management Mode
//
//      Pentium Pro instructions
//
NN_cmova,               // Move if Above (CF=0 & ZF=0)
NN_cmovb,               // Move if Below (CF=1)
NN_cmovbe,              // Move if Below or Equal (CF=1 | ZF=1)
NN_cmovg,               // Move if Greater (ZF=0 & SF=OF)
NN_cmovge,              // Move if Greater or Equal (SF=OF)
NN_cmovl,               // Move if Less (SF!=OF)
NN_cmovle,              // Move if Less or Equal (ZF=1 | SF!=OF)
NN_cmovnb,              // Move if Not Below (CF=0)
NN_cmovno,              // Move if Not Overflow (OF=0)
NN_cmovnp,              // Move if Not Parity (PF=0)
NN_cmovns,              // Move if Not Sign (SF=0)
NN_cmovnz,              // Move if Not Zero (ZF=0)
NN_cmovo,               // Move if Overflow (OF=1)
NN_cmovp,               // Move if Parity (PF=1)
NN_cmovs,               // Move if Sign (SF=1)
NN_cmovz,               // Move if Zero (ZF=1)
NN_fcmovb,              // Floating Move if Below
NN_fcmove,              // Floating Move if Equal
NN_fcmovbe,             // Floating Move if Below or Equal
NN_fcmovu,              // Floating Move if Unordered
NN_fcmovnb,             // Floating Move if Not Below
NN_fcmovne,             // Floating Move if Not Equal
NN_fcmovnbe,            // Floating Move if Not Below or Equal
NN_fcmovnu,             // Floating Move if Not Unordered
NN_fcomi,               // FP Compare, result in EFLAGS
NN_fucomi,              // FP Unordered Compare, result in EFLAGS
NN_fcomip,              // FP Compare, result in EFLAGS, pop stack
NN_fucomip,             // FP Unordered Compare, result in EFLAGS, pop stack
NN_rdpmc,               // Read Performance Monitor Counter
//
//      FPP instructuions
//
NN_fld,                 // Load Real
NN_fst,                 // Store Real
NN_fstp,                // Store Real and Pop
NN_fxch,                // Exchange Registers
NN_fild,                // Load Integer
NN_fist,                // Store Integer
NN_fistp,               // Store Integer and Pop
NN_fbld,                // Load BCD
NN_fbstp,               // Store BCD and Pop
NN_fadd,                // Add Real
NN_faddp,               // Add Real and Pop
NN_fiadd,               // Add Integer
NN_fsub,                // Subtract Real
NN_fsubp,               // Subtract Real and Pop
NN_fisub,               // Subtract Integer
NN_fsubr,               // Subtract Real Reversed
NN_fsubrp,              // Subtract Real Reversed and Pop
NN_fisubr,              // Subtract Integer Reversed
NN_fmul,                // Multiply Real
NN_fmulp,               // Multiply Real and Pop
NN_fimul,               // Multiply Integer
NN_fdiv,                // Divide Real
NN_fdivp,               // Divide Real and Pop
NN_fidiv,               // Divide Integer
NN_fdivr,               // Divide Real Reversed
NN_fdivrp,              // Divide Real Reversed and Pop
NN_fidivr,              // Divide Integer Reversed
NN_fsqrt,               // Square Root
NN_fscale,              // Scale:  st(0) <- st(0) * 2^st(1)
NN_fprem,               // Partial Remainder
NN_frndint,             // Round to Integer
NN_fxtract,             // Extract exponent and significand
NN_fabs,                // Absolute value
NN_fchs,                // Change Sign
NN_fcom,                // Compare Real
NN_fcomp,               // Compare Real and Pop
NN_fcompp,              // Compare Real and Pop Twice
NN_ficom,               // Compare Integer
NN_ficomp,              // Compare Integer and Pop
NN_ftst,                // Test
NN_fxam,                // Examine
NN_fptan,               // Partial tangent
NN_fpatan,              // Partial arctangent
NN_f2xm1,               // 2^x - 1
NN_fyl2x,               // Y * lg2(X)
NN_fyl2xp1,             // Y * lg2(X+1)
NN_fldz,                // Load +0.0
NN_fld1,                // Load +1.0
NN_fldpi,               // Load PI=3.14...
NN_fldl2t,              // Load lg2(10)
NN_fldl2e,              // Load lg2(e)
NN_fldlg2,              // Load lg10(2)
NN_fldln2,              // Load ln(2)
NN_finit,               // Initialize Processor
NN_fninit,              // Initialize Processor (no wait)
NN_fsetpm,              // Set Protected Mode
NN_fldcw,               // Load Control Word
NN_fstcw,               // Store Control Word
NN_fnstcw,              // Store Control Word (no wait)
NN_fstsw,               // Store Status Word
NN_fnstsw,              // Store Status Word (no wait)
NN_fclex,               // Clear Exceptions
NN_fnclex,              // Clear Exceptions (no wait)
NN_fstenv,              // Store Environment
NN_fnstenv,             // Store Environment (no wait)
NN_fldenv,              // Load Environment
NN_fsave,               // Save State
NN_fnsave,              // Save State (no wait)
NN_frstor,              // Restore State
NN_fincstp,             // Increment Stack Pointer
NN_fdecstp,             // Decrement Stack Pointer
NN_ffree,               // Free Register
NN_fnop,                // No Operation
NN_feni,                // (8087 only)
NN_fneni,               // (no wait) (8087 only)
NN_fdisi,               // (8087 only)
NN_fndisi,              // (no wait) (8087 only)
//
//      80387 instructions
//
NN_fprem1,              // Partial Remainder ( < half )
NN_fsincos,             // t<-cos(st); st<-sin(st); push t
NN_fsin,                // Sine
NN_fcos,                // Cosine
NN_fucom,               // Compare Unordered Real
NN_fucomp,              // Compare Unordered Real and Pop
NN_fucompp,             // Compare Unordered Real and Pop Twice
//
//      Instructions added 28.02.96
//
NN_setalc,              // Set AL to Carry Flag
NN_svdc,                // Save Register and Descriptor
NN_rsdc,                // Restore Register and Descriptor
NN_svldt,               // Save LDTR and Descriptor
NN_rsldt,               // Restore LDTR and Descriptor
NN_svts,                // Save TR and Descriptor
NN_rsts,                // Restore TR and Descriptor
NN_icebp,               // ICE Break Point
NN_loadall,             // Load the entire CPU state from ES:EDI
//
//      MMX instructions
//
NN_emms,                // Empty MMX state
NN_movd,                // Move 32 bits
NN_movq,                // Move 64 bits
NN_packsswb,            // Pack with Signed Saturation (Word->Byte)
NN_packssdw,            // Pack with Signed Saturation (Dword->Word)
NN_packuswb,            // Pack with Unsigned Saturation (Word->Byte)
NN_paddb,               // Packed Add Byte
NN_paddw,               // Packed Add Word
NN_paddd,               // Packed Add Dword
NN_paddsb,              // Packed Add with Saturation (Byte)
NN_paddsw,              // Packed Add with Saturation (Word)
NN_paddusb,             // Packed Add Unsigned with Saturation (Byte)
NN_paddusw,             // Packed Add Unsigned with Saturation (Word)
NN_pand,                // Bitwise Logical And
NN_pandn,               // Bitwise Logical And Not
NN_pcmpeqb,             // Packed Compare for Equal (Byte)
NN_pcmpeqw,             // Packed Compare for Equal (Word)
NN_pcmpeqd,             // Packed Compare for Equal (Dword)
NN_pcmpgtb,             // Packed Compare for Greater Than (Byte)
NN_pcmpgtw,             // Packed Compare for Greater Than (Word)
NN_pcmpgtd,             // Packed Compare for Greater Than (Dword)
NN_pmaddwd,             // Packed Multiply and Add
NN_pmulhw,              // Packed Multiply High
NN_pmullw,              // Packed Multiply Low
NN_por,                 // Bitwise Logical Or
NN_psllw,               // Packed Shift Left Logical (Word)
NN_pslld,               // Packed Shift Left Logical (Dword)
NN_psllq,               // Packed Shift Left Logical (Qword)
NN_psraw,               // Packed Shift Right Arithmetic (Word)
NN_psrad,               // Packed Shift Right Arithmetic (Dword)
NN_psrlw,               // Packed Shift Right Logical (Word)
NN_psrld,               // Packed Shift Right Logical (Dword)
NN_psrlq,               // Packed Shift Right Logical (Qword)
NN_psubb,               // Packed Subtract Byte
NN_psubw,               // Packed Subtract Word
NN_psubd,               // Packed Subtract Dword
NN_psubsb,              // Packed Subtract with Saturation (Byte)
NN_psubsw,              // Packed Subtract with Saturation (Word)
NN_psubusb,             // Packed Subtract Unsigned with Saturation (Byte)
NN_psubusw,             // Packed Subtract Unsigned with Saturation (Word)
NN_punpckhbw,           // Unpack High Packed Data (Byte->Word)
NN_punpckhwd,           // Unpack High Packed Data (Word->Dword)
NN_punpckhdq,           // Unpack High Packed Data (Dword->Qword)
NN_punpcklbw,           // Unpack Low Packed Data (Byte->Word)
NN_punpcklwd,           // Unpack Low Packed Data (Word->Dword)
NN_punpckldq,           // Unpack Low Packed Data (Dword->Qword)
NN_pxor,                // Bitwise Logical Exclusive Or
//
//      Undocumented Deschutes processor instructions
//
NN_fxsave,              // Fast save FP context
NN_fxrstor,             // Fast restore FP context
//      Pentium II instructions
NN_sysenter,            // Fast Transition to System Call Entry Point
NN_sysexit,             // Fast Transition from System Call Entry Point
//      3DNow! instructions
NN_pavgusb,             // Packed 8-bit Unsigned Integer Averaging
NN_pfadd,               // Packed Floating-Point Addition
NN_pfsub,               // Packed Floating-Point Subtraction
NN_pfsubr,              // Packed Floating-Point Reverse Subtraction
NN_pfacc,               // Packed Floating-Point Accumulate
NN_pfcmpge,             // Packed Floating-Point Comparison, Greater or Equal
NN_pfcmpgt,             // Packed Floating-Point Comparison, Greater
NN_pfcmpeq,             // Packed Floating-Point Comparison, Equal
NN_pfmin,               // Packed Floating-Point Minimum
NN_pfmax,               // Packed Floating-Point Maximum
NN_pi2fd,               // Packed 32-bit Integer to Floating-Point
NN_pf2id,               // Packed Floating-Point to 32-bit Integer
NN_pfrcp,               // Packed Floating-Point Reciprocal Approximation
NN_pfrsqrt,             // Packed Floating-Point Reciprocal Square Root Approximation
NN_pfmul,               // Packed Floating-Point Multiplication
NN_pfrcpit1,            // Packed Floating-Point Reciprocal First Iteration Step
NN_pfrsqit1,            // Packed Floating-Point Reciprocal Square Root First Iteration Step
NN_pfrcpit2,            // Packed Floating-Point Reciprocal Second Iteration Step
NN_pmulhrw,             // Packed Floating-Point 16-bit Integer Multiply with rounding
NN_femms,               // Faster entry/exit of the MMX or floating-point state
NN_prefetch,            // Prefetch at least a 32-byte line into L1 data cache
NN_prefetchw,           // Prefetch processor cache line into L1 data cache (mark as modified)
//      Pentium III instructions
NN_addps,               // Packed Single-FP Add
NN_addss,               // Scalar Single-FP Add
NN_andnps,              // Bitwise Logical And Not for Single-FP
NN_andps,               // Bitwise Logical And for Single-FP
NN_cmpps,               // Packed Single-FP Compare
NN_cmpss,               // Scalar Single-FP Compare
NN_comiss,              // Scalar Ordered Single-FP Compare and Set EFLAGS
NN_cvtpi2ps,            // Packed signed INT32 to Packed Single-FP conversion
NN_cvtps2pi,            // Packed Single-FP to Packed INT32 conversion
NN_cvtsi2ss,            // Scalar signed INT32 to Single-FP conversion
NN_cvtss2si,            // Scalar Single-FP to signed INT32 conversion
NN_cvttps2pi,           // Packed Single-FP to Packed INT32 conversion (truncate)
NN_cvttss2si,           // Scalar Single-FP to signed INT32 conversion (truncate)
NN_divps,               // Packed Single-FP Divide
NN_divss,               // Scalar Single-FP Divide
NN_ldmxcsr,             // Load Streaming SIMD Extensions Technology Control/Status Register
NN_maxps,               // Packed Single-FP Maximum
NN_maxss,               // Scalar Single-FP Maximum
NN_minps,               // Packed Single-FP Minimum
NN_minss,               // Scalar Single-FP Minimum
NN_movaps,              // Move Aligned Four Packed Single-FP
NN_movhlps,             // Move High to Low Packed Single-FP
NN_movhps,              // Move High Packed Single-FP
NN_movlhps,             // Move Low to High Packed Single-FP
NN_movlps,              // Move Low Packed Single-FP
NN_movmskps,            // Move Mask to Register
NN_movss,               // Move Scalar Single-FP
NN_movups,              // Move Unaligned Four Packed Single-FP
NN_mulps,               // Packed Single-FP Multiply
NN_mulss,               // Scalar Single-FP Multiply
NN_orps,                // Bitwise Logical OR for Single-FP Data
NN_rcpps,               // Packed Single-FP Reciprocal
NN_rcpss,               // Scalar Single-FP Reciprocal
NN_rsqrtps,             // Packed Single-FP Square Root Reciprocal
NN_rsqrtss,             // Scalar Single-FP Square Root Reciprocal
NN_shufps,              // Shuffle Single-FP
NN_sqrtps,              // Packed Single-FP Square Root
NN_sqrtss,              // Scalar Single-FP Square Root
NN_stmxcsr,             // Store Streaming SIMD Extensions Technology Control/Status Register
NN_subps,               // Packed Single-FP Subtract
NN_subss,               // Scalar Single-FP Subtract
NN_ucomiss,             // Scalar Unordered Single-FP Compare and Set EFLAGS
NN_unpckhps,            // Unpack High Packed Single-FP Data
NN_unpcklps,            // Unpack Low Packed Single-FP Data
NN_xorps,               // Bitwise Logical XOR for Single-FP Data
NN_pavgb,               // Packed Average (Byte)
NN_pavgw,               // Packed Average (Word)
NN_pextrw,              // Extract Word
NN_pinsrw,              // Insert Word
NN_pmaxsw,              // Packed Signed Integer Word Maximum
NN_pmaxub,              // Packed Unsigned Integer Byte Maximum
NN_pminsw,              // Packed Signed Integer Word Minimum
NN_pminub,              // Packed Unsigned Integer Byte Minimum
NN_pmovmskb,            // Move Byte Mask to Integer
NN_pmulhuw,             // Packed Multiply High Unsigned
NN_psadbw,              // Packed Sum of Absolute Differences
NN_pshufw,              // Packed Shuffle Word
NN_maskmovq,            // Byte Mask write
NN_movntps,             // Move Aligned Four Packed Single-FP Non Temporal
NN_movntq,              // Move 64 Bits Non Temporal
NN_prefetcht0,          // Prefetch to all cache levels
NN_prefetcht1,          // Prefetch to all cache levels
NN_prefetcht2,          // Prefetch to L2 cache
NN_prefetchnta,         // Prefetch to L1 cache
NN_sfence,              // Store Fence
// Pentium III Pseudo instructions
NN_cmpeqps,             // Packed Single-FP Compare EQ
NN_cmpltps,             // Packed Single-FP Compare LT
NN_cmpleps,             // Packed Single-FP Compare LE
NN_cmpunordps,          // Packed Single-FP Compare UNORD
NN_cmpneqps,            // Packed Single-FP Compare NOT EQ
NN_cmpnltps,            // Packed Single-FP Compare NOT LT
NN_cmpnleps,            // Packed Single-FP Compare NOT LE
NN_cmpordps,            // Packed Single-FP Compare ORDERED
NN_cmpeqss,             // Scalar Single-FP Compare EQ
NN_cmpltss,             // Scalar Single-FP Compare LT
NN_cmpless,             // Scalar Single-FP Compare LE
NN_cmpunordss,          // Scalar Single-FP Compare UNORD
NN_cmpneqss,            // Scalar Single-FP Compare NOT EQ
NN_cmpnltss,            // Scalar Single-FP Compare NOT LT
NN_cmpnless,            // Scalar Single-FP Compare NOT LE
NN_cmpordss,            // Scalar Single-FP Compare ORDERED
// AMD K7 instructions
NN_pf2iw,               // Packed Floating-Point to Integer with Sign Extend
NN_pfnacc,              // Packed Floating-Point Negative Accumulate
NN_pfpnacc,             // Packed Floating-Point Mixed Positive-Negative Accumulate
NN_pi2fw,               // Packed 16-bit Integer to Floating-Point
NN_pswapd,              // Packed Swap Double Word
// Undocumented FP instructions (thanks to norbert.juffa@amd.com)
NN_fstp1,               // Alias of Store Real and Pop
NN_fcom2,               // Alias of Compare Real
NN_fcomp3,              // Alias of Compare Real and Pop
NN_fxch4,               // Alias of Exchange Registers
NN_fcomp5,              // Alias of Compare Real and Pop
NN_ffreep,              // Free Register and Pop
NN_fxch7,               // Alias of Exchange Registers
NN_fstp8,               // Alias of Store Real and Pop
NN_fstp9,               // Alias of Store Real and Pop
// Pentium 4 instructions
NN_addpd,               // Add Packed Double-Precision Floating-Point Values
NN_addsd,               // Add Scalar Double-Precision Floating-Point Values
NN_andnpd,              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
NN_andpd,               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
NN_clflush,             // Flush Cache Line
NN_cmppd,               // Compare Packed Double-Precision Floating-Point Values
NN_cmpsd,               // Compare Scalar Double-Precision Floating-Point Values
NN_comisd,              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
NN_cvtdq2pd,            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
NN_cvtdq2ps,            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
NN_cvtpd2dq,            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvtpd2pi,            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvtpd2ps,            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
NN_cvtpi2pd,            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
NN_cvtps2dq,            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvtps2pd,            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
NN_cvtsd2si,            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
NN_cvtsd2ss,            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
NN_cvtsi2sd,            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
NN_cvtss2sd,            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
NN_cvttpd2dq,           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvttpd2pi,           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvttps2dq,           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
NN_cvttsd2si,           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
NN_divpd,               // Divide Packed Double-Precision Floating-Point Values
NN_divsd,               // Divide Scalar Double-Precision Floating-Point Values
NN_lfence,              // Load Fence
NN_maskmovdqu,          // Store Selected Bytes of Double Quadword
NN_maxpd,               // Return Maximum Packed Double-Precision Floating-Point Values
NN_maxsd,               // Return Maximum Scalar Double-Precision Floating-Point Value
NN_mfence,              // Memory Fence
NN_minpd,               // Return Minimum Packed Double-Precision Floating-Point Values
NN_minsd,               // Return Minimum Scalar Double-Precision Floating-Point Value
NN_movapd,              // Move Aligned Packed Double-Precision Floating-Point Values
NN_movdq2q,             // Move Quadword from XMM to MMX Register
NN_movdqa,              // Move Aligned Double Quadword
NN_movdqu,              // Move Unaligned Double Quadword
NN_movhpd,              // Move High Packed Double-Precision Floating-Point Values
NN_movlpd,              // Move Low Packed Double-Precision Floating-Point Values
NN_movmskpd,            // Extract Packed Double-Precision Floating-Point Sign Mask
NN_movntdq,             // Store Double Quadword Using Non-Temporal Hint
NN_movnti,              // Store Doubleword Using Non-Temporal Hint
NN_movntpd,             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
NN_movq2dq,             // Move Quadword from MMX to XMM Register
NN_movsd,               // Move Scalar Double-Precision Floating-Point Values
NN_movupd,              // Move Unaligned Packed Double-Precision Floating-Point Values
NN_mulpd,               // Multiply Packed Double-Precision Floating-Point Values
NN_mulsd,               // Multiply Scalar Double-Precision Floating-Point Values
NN_orpd,                // Bitwise Logical OR of Double-Precision Floating-Point Values
NN_paddq,               // Add Packed Quadword Integers
NN_pause,               // Spin Loop Hint
NN_pmuludq,             // Multiply Packed Unsigned Doubleword Integers
NN_pshufd,              // Shuffle Packed Doublewords
NN_pshufhw,             // Shuffle Packed High Words
NN_pshuflw,             // Shuffle Packed Low Words
NN_pslldq,              // Shift Double Quadword Left Logical
NN_psrldq,              // Shift Double Quadword Right Logical
NN_psubq,               // Subtract Packed Quadword Integers
NN_punpckhqdq,          // Unpack High Data
NN_punpcklqdq,          // Unpack Low Data
NN_shufpd,              // Shuffle Packed Double-Precision Floating-Point Values
NN_sqrtpd,              // Compute Square Roots of Packed Double-Precision Floating-Point Values
NN_sqrtsd,              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
NN_subpd,               // Subtract Packed Double-Precision Floating-Point Values
NN_subsd,               // Subtract Scalar Double-Precision Floating-Point Values
NN_ucomisd,             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
NN_unpckhpd,            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
NN_unpcklpd,            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
NN_xorpd,               // Bitwise Logical OR of Double-Precision Floating-Point Values
// AMD syscall/sysret instructions
NN_syscall,             // Low latency system call
NN_sysret,              // Return from system call
// AMD64 instructions
NN_swapgs,              // Exchange GS base with KernelGSBase MSR
// New Pentium instructions (SSE3)
NN_movddup,             // Move One Double-FP and Duplicate
NN_movshdup,            // Move Packed Single-FP High and Duplicate
NN_movsldup,            // Move Packed Single-FP Low and Duplicate
// Missing AMD64 instructions
NN_movsxd,              // Move with Sign-Extend Doubleword
NN_cmpxchg16b,          // Compare and Exchange 16 Bytes
// SSE3 instructions
NN_addsubpd,            // Add /Sub packed DP FP numbers
NN_addsubps,            // Add /Sub packed SP FP numbers
NN_haddpd,              // Add horizontally packed DP FP numbers
NN_haddps,              // Add horizontally packed SP FP numbers
NN_hsubpd,              // Sub horizontally packed DP FP numbers
NN_hsubps,              // Sub horizontally packed SP FP numbers
NN_monitor,             // Set up a linear address range to be monitored by hardware
NN_mwait,               // Wait until write-back store performed within the range specified by the MONITOR instruction
NN_fisttp,              // Store ST in intXX (chop) and pop
NN_lddqu,               // Load unaligned integer 128-bit
// SSSE3 instructions
NN_psignb,              // Packed SIGN Byte
NN_psignw,              // Packed SIGN Word
NN_psignd,              // Packed SIGN Doubleword
NN_pshufb,              // Packed Shuffle Bytes
NN_pmulhrsw,            // Packed Multiply High with Round and Scale
NN_pmaddubsw,           // Multiply and Add Packed Signed and Unsigned Bytes
NN_phsubsw,             // Packed Horizontal Subtract and Saturate
NN_phaddsw,             // Packed Horizontal Add and Saturate
NN_phaddw,              // Packed Horizontal Add Word
NN_phaddd,              // Packed Horizontal Add Doubleword
NN_phsubw,              // Packed Horizontal Subtract Word
NN_phsubd,              // Packed Horizontal Subtract Doubleword
NN_palignr,             // Packed Align Right
NN_pabsb,               // Packed Absolute Value Byte
NN_pabsw,               // Packed Absolute Value Word
NN_pabsd,               // Packed Absolute Value Doubleword
// VMX instructions
NN_vmcall,              // Call to VM Monitor
NN_vmclear,             // Clear Virtual Machine Control Structure
NN_vmlaunch,            // Launch Virtual Machine
NN_vmresume,            // Resume Virtual Machine
NN_vmptrld,             // Load Pointer to Virtual Machine Control Structure
NN_vmptrst,             // Store Pointer to Virtual Machine Control Structure
NN_vmread,              // Read Field from Virtual Machine Control Structure
NN_vmwrite,             // Write Field from Virtual Machine Control Structure
NN_vmxoff,              // Leave VMX Operation
NN_vmxon,               // Enter VMX Operation
// Undefined Instruction
NN_ud2,                 // Undefined Instruction
// Added with x86-64
NN_rdtscp,              // Read Time-Stamp Counter and Processor ID
// Geode LX 3DNow! extensions
NN_pfrcpv,              // Reciprocal Approximation for a Pair of 32-bit Floats
NN_pfrsqrtv,            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats
// SSE2 pseudoinstructions
NN_cmpeqpd,             // Packed Double-FP Compare EQ
NN_cmpltpd,             // Packed Double-FP Compare LT
NN_cmplepd,             // Packed Double-FP Compare LE
NN_cmpunordpd,          // Packed Double-FP Compare UNORD
NN_cmpneqpd,            // Packed Double-FP Compare NOT EQ
NN_cmpnltpd,            // Packed Double-FP Compare NOT LT
NN_cmpnlepd,            // Packed Double-FP Compare NOT LE
NN_cmpordpd,            // Packed Double-FP Compare ORDERED
NN_cmpeqsd,             // Scalar Double-FP Compare EQ
NN_cmpltsd,             // Scalar Double-FP Compare LT
NN_cmplesd,             // Scalar Double-FP Compare LE
NN_cmpunordsd,          // Scalar Double-FP Compare UNORD
NN_cmpneqsd,            // Scalar Double-FP Compare NOT EQ
NN_cmpnltsd,            // Scalar Double-FP Compare NOT LT
NN_cmpnlesd,            // Scalar Double-FP Compare NOT LE
NN_cmpordsd,            // Scalar Double-FP Compare ORDERED
// SSSE4.1 instructions
NN_blendpd,              // Blend Packed Double Precision Floating-Point Values
NN_blendps,              // Blend Packed Single Precision Floating-Point Values
NN_blendvpd,             // Variable Blend Packed Double Precision Floating-Point Values
NN_blendvps,             // Variable Blend Packed Single Precision Floating-Point Values
NN_dppd,                 // Dot Product of Packed Double Precision Floating-Point Values
NN_dpps,                 // Dot Product of Packed Single Precision Floating-Point Values
NN_extractps,            // Extract Packed Single Precision Floating-Point Value
NN_insertps,             // Insert Packed Single Precision Floating-Point Value
NN_movntdqa,             // Load Double Quadword Non-Temporal Aligned Hint
NN_mpsadbw,              // Compute Multiple Packed Sums of Absolute Difference
NN_packusdw,             // Pack with Unsigned Saturation
NN_pblendvb,             // Variable Blend Packed Bytes
NN_pblendw,              // Blend Packed Words
NN_pcmpeqq,              // Compare Packed Qword Data for Equal
NN_pextrb,               // Extract Byte
NN_pextrd,               // Extract Dword
NN_pextrq,               // Extract Qword
NN_phminposuw,           // Packed Horizontal Word Minimum
NN_pinsrb,               // Insert Byte
NN_pinsrd,               // Insert Dword
NN_pinsrq,               // Insert Qword
NN_pmaxsb,               // Maximum of Packed Signed Byte Integers
NN_pmaxsd,               // Maximum of Packed Signed Dword Integers
NN_pmaxud,               // Maximum of Packed Unsigned Dword Integers
NN_pmaxuw,               // Maximum of Packed Word Integers
NN_pminsb,               // Minimum of Packed Signed Byte Integers
NN_pminsd,               // Minimum of Packed Signed Dword Integers
NN_pminud,               // Minimum of Packed Unsigned Dword Integers
NN_pminuw,               // Minimum of Packed Word Integers
NN_pmovsxbw,             // Packed Move with Sign Extend
NN_pmovsxbd,             // Packed Move with Sign Extend
NN_pmovsxbq,             // Packed Move with Sign Extend
NN_pmovsxwd,             // Packed Move with Sign Extend
NN_pmovsxwq,             // Packed Move with Sign Extend
NN_pmovsxdq,             // Packed Move with Sign Extend
NN_pmovzxbw,             // Packed Move with Zero Extend
NN_pmovzxbd,             // Packed Move with Zero Extend
NN_pmovzxbq,             // Packed Move with Zero Extend
NN_pmovzxwd,             // Packed Move with Zero Extend
NN_pmovzxwq,             // Packed Move with Zero Extend
NN_pmovzxdq,             // Packed Move with Zero Extend
NN_pmuldq,               // Multiply Packed Signed Dword Integers
NN_pmulld,               // Multiply Packed Signed Dword Integers and Store Low Result
NN_ptest,                // Logical Compare
NN_roundpd,              // Round Packed Double Precision Floating-Point Values
NN_roundps,              // Round Packed Single Precision Floating-Point Values
NN_roundsd,              // Round Scalar Double Precision Floating-Point Values
NN_roundss,              // Round Scalar Single Precision Floating-Point Values
// SSSE4.2 instructions
NN_crc32,                // Accumulate CRC32 Value
NN_pcmpestri,            // Packed Compare Explicit Length Strings, Return Index
NN_pcmpestrm,            // Packed Compare Explicit Length Strings, Return Mask
NN_pcmpistri,            // Packed Compare Implicit Length Strings, Return Index
NN_pcmpistrm,            // Packed Compare Implicit Length Strings, Return Mask
NN_pcmpgtq,              // Compare Packed Data for Greater Than
NN_popcnt,               // Return the Count of Number of Bits Set to 1
// AMD SSE4a instructions
NN_extrq,                // Extract Field From Register
NN_insertq,              // Insert Field
NN_movntsd,              // Move Non-Temporal Scalar Double-Precision Floating-Point
NN_movntss,              // Move Non-Temporal Scalar Single-Precision Floating-Point
NN_lzcnt,                // Leading Zero Count
// xsave/xrstor instructions
NN_xgetbv,               // Get Value of Extended Control Register
NN_xrstor,               // Restore Processor Extended States
NN_xsave,                // Save Processor Extended States
NN_xsetbv,               // Set Value of Extended Control Register
// Intel Safer Mode Extensions (SMX)
NN_getsec,               // Safer Mode Extensions (SMX) Instruction
// AMD-V Virtualization ISA Extension
NN_clgi,                 // Clear Global Interrupt Flag
NN_invlpga,              // Invalidate TLB Entry in a Specified ASID
NN_skinit,               // Secure Init and Jump with Attestation
NN_stgi,                 // Set Global Interrupt Flag
NN_vmexit,               // Stop Executing Guest, Begin Executing Host
NN_vmload,               // Load State from VMCB
NN_vmmcall,              // Call VMM
NN_vmrun,                // Run Virtual Machine
NN_vmsave,               // Save State to VMCB
// VMX+ instructions
NN_invept,               // Invalidate Translations Derived from EPT
NN_invvpid,              // Invalidate Translations Based on VPID
// Intel Atom instructions
NN_movbe,                // Move Data After Swapping Bytes
// Intel AES instructions
NN_aesenc,                // Perform One Round of an AES Encryption Flow
NN_aesenclast,            // Perform the Last Round of an AES Encryption Flow
NN_aesdec,                // Perform One Round of an AES Decryption Flow
NN_aesdeclast,            // Perform the Last Round of an AES Decryption Flow
NN_aesimc,                // Perform the AES InvMixColumn Transformation
NN_aeskeygenassist,       // AES Round Key Generation Assist
// Carryless multiplication
NN_pclmulqdq,            // Carry-Less Multiplication Quadword
// Returns modifies by operand size prefixes
NN_retnw,               // Return Near from Procedure (use16)
NN_retnd,               // Return Near from Procedure (use32)
NN_retnq,               // Return Near from Procedure (use64)
NN_retfw,               // Return Far from Procedure (use16)
NN_retfd,               // Return Far from Procedure (use32)
NN_retfq,               // Return Far from Procedure (use64)
// RDRAND support
NN_rdrand,              // Read Random Number
// new GPR instructions
NN_adcx,                 // Unsigned Integer Addition of Two Operands with Carry Flag
NN_adox,                 // Unsigned Integer Addition of Two Operands with Overflow Flag
NN_andn,                 // Logical AND NOT
NN_bextr,                // Bit Field Extract
NN_blsi,                 // Extract Lowest Set Isolated Bit
NN_blsmsk,               // Get Mask Up to Lowest Set Bit
NN_blsr,                 // Reset Lowest Set Bit
NN_bzhi,                 // Zero High Bits Starting with Specified Bit Position
NN_clac,                 // Clear AC Flag in EFLAGS Register
NN_mulx,                 // Unsigned Multiply Without Affecting Flags
NN_pdep,                 // Parallel Bits Deposit
NN_pext,                 // Parallel Bits Extract
NN_rorx,                 // Rotate Right Logical Without Affecting Flags
NN_sarx,                 // Shift Arithmetically Right Without Affecting Flags
NN_shlx,                 // Shift Logically Left Without Affecting Flags
NN_shrx,                 // Shift Logically Right Without Affecting Flags
NN_stac,                 // Set AC Flag in EFLAGS Register
NN_tzcnt,                // Count the Number of Trailing Zero Bits
NN_xsaveopt,             // Save Processor Extended States Optimized
NN_invpcid,              // Invalidate Processor Context ID
NN_rdseed,               // Read Random Seed
NN_rdfsbase,             // Read FS Segment Base
NN_rdgsbase,             // Read GS Segment Base
NN_wrfsbase,             // Write FS Segment Base
NN_wrgsbase,             // Write GS Segment Base
// new AVX instructions
NN_vaddpd,               // Add Packed Double-Precision Floating-Point Values
NN_vaddps,               // Packed Single-FP Add
NN_vaddsd,               // Add Scalar Double-Precision Floating-Point Values
NN_vaddss,               // Scalar Single-FP Add
NN_vaddsubpd,            // Add /Sub packed DP FP numbers
NN_vaddsubps,            // Add /Sub packed SP FP numbers
NN_vaesdec,              // Perform One Round of an AES Decryption Flow
NN_vaesdeclast,          // Perform the Last Round of an AES Decryption Flow
NN_vaesenc,              // Perform One Round of an AES Encryption Flow
NN_vaesenclast,          // Perform the Last Round of an AES Encryption Flow
NN_vaesimc,              // Perform the AES InvMixColumn Transformation
NN_vaeskeygenassist,     // AES Round Key Generation Assist
NN_vandnpd,              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
NN_vandnps,              // Bitwise Logical And Not for Single-FP
NN_vandpd,               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
NN_vandps,               // Bitwise Logical And for Single-FP
NN_vblendpd,             // Blend Packed Double Precision Floating-Point Values
NN_vblendps,             // Blend Packed Single Precision Floating-Point Values
NN_vblendvpd,            // Variable Blend Packed Double Precision Floating-Point Values
NN_vblendvps,            // Variable Blend Packed Single Precision Floating-Point Values
NN_vbroadcastf128,       // Broadcast 128 Bits of Floating-Point Data
NN_vbroadcasti128,       // Broadcast 128 Bits of Integer Data
NN_vbroadcastsd,         // Broadcast Double-Precision Floating-Point Element
NN_vbroadcastss,         // Broadcast Single-Precision Floating-Point Element
NN_vcmppd,               // Compare Packed Double-Precision Floating-Point Values
NN_vcmpps,               // Packed Single-FP Compare
NN_vcmpsd,               // Compare Scalar Double-Precision Floating-Point Values
NN_vcmpss,               // Scalar Single-FP Compare
NN_vcomisd,              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
NN_vcomiss,              // Scalar Ordered Single-FP Compare and Set EFLAGS
NN_vcvtdq2pd,            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
NN_vcvtdq2ps,            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
NN_vcvtpd2dq,            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_vcvtpd2ps,            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
NN_vcvtph2ps,            // Convert 16-bit FP Values to Single-Precision FP Values
NN_vcvtps2dq,            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
NN_vcvtps2pd,            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
NN_vcvtps2ph,            // Convert Single-Precision FP value to 16-bit FP value
NN_vcvtsd2si,            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
NN_vcvtsd2ss,            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
NN_vcvtsi2sd,            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
NN_vcvtsi2ss,            // Scalar signed INT32 to Single-FP conversion
NN_vcvtss2sd,            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
NN_vcvtss2si,            // Scalar Single-FP to signed INT32 conversion
NN_vcvttpd2dq,           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
NN_vcvttps2dq,           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
NN_vcvttsd2si,           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
NN_vcvttss2si,           // Scalar Single-FP to signed INT32 conversion (truncate)
NN_vdivpd,               // Divide Packed Double-Precision Floating-Point Values
NN_vdivps,               // Packed Single-FP Divide
NN_vdivsd,               // Divide Scalar Double-Precision Floating-Point Values
NN_vdivss,               // Scalar Single-FP Divide
NN_vdppd,                // Dot Product of Packed Double Precision Floating-Point Values
NN_vdpps,                // Dot Product of Packed Single Precision Floating-Point Values
NN_vextractf128,         // Extract Packed Floating-Point Values
NN_vextracti128,         // Extract Packed Integer Values
NN_vextractps,           // Extract Packed Floating-Point Values
NN_vfmadd132pd,          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfmadd132ps,          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfmadd132sd,          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfmadd132ss,          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfmadd213pd,          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfmadd213ps,          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfmadd213sd,          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfmadd213ss,          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfmadd231pd,          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfmadd231ps,          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfmadd231sd,          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfmadd231ss,          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfmaddsub132pd,       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
NN_vfmaddsub132ps,       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
NN_vfmaddsub213pd,       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
NN_vfmaddsub213ps,       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
NN_vfmaddsub231pd,       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
NN_vfmaddsub231ps,       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
NN_vfmsub132pd,          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfmsub132ps,          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfmsub132sd,          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfmsub132ss,          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vfmsub213pd,          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfmsub213ps,          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfmsub213sd,          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfmsub213ss,          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vfmsub231pd,          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfmsub231ps,          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfmsub231sd,          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfmsub231ss,          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vfmsubadd132pd,       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
NN_vfmsubadd132ps,       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
NN_vfmsubadd213pd,       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
NN_vfmsubadd213ps,       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
NN_vfmsubadd231pd,       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
NN_vfmsubadd231ps,       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
NN_vfnmadd132pd,         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfnmadd132ps,         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfnmadd132sd,         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfnmadd132ss,         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfnmadd213pd,         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfnmadd213ps,         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfnmadd213sd,         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfnmadd213ss,         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfnmadd231pd,         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
NN_vfnmadd231ps,         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
NN_vfnmadd231sd,         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
NN_vfnmadd231ss,         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
NN_vfnmsub132pd,         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfnmsub132ps,         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfnmsub132sd,         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfnmsub132ss,         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vfnmsub213pd,         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfnmsub213ps,         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfnmsub213sd,         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfnmsub213ss,         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vfnmsub231pd,         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
NN_vfnmsub231ps,         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
NN_vfnmsub231sd,         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
NN_vfnmsub231ss,         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
NN_vgatherdps,           // Gather Packed SP FP Values Using Signed Dword Indices
NN_vgatherdpd,           // Gather Packed DP FP Values Using Signed Dword Indices
NN_vgatherqps,           // Gather Packed SP FP Values Using Signed Qword Indices
NN_vgatherqpd,           // Gather Packed DP FP Values Using Signed Qword Indices
NN_vhaddpd,              // Add horizontally packed DP FP numbers
NN_vhaddps,              // Add horizontally packed SP FP numbers
NN_vhsubpd,              // Sub horizontally packed DP FP numbers
NN_vhsubps,              // Sub horizontally packed SP FP numbers
NN_vinsertf128,          // Insert Packed Floating-Point Values
NN_vinserti128,          // Insert Packed Integer Values
NN_vinsertps,            // Insert Packed Single Precision Floating-Point Value
NN_vlddqu,               // Load Unaligned Packed Integer Values
NN_vldmxcsr,             // Load Streaming SIMD Extensions Technology Control/Status Register
NN_vmaskmovdqu,          // Store Selected Bytes of Double Quadword with NT Hint
NN_vmaskmovpd,           // Conditionally Load Packed Double-Precision Floating-Point Values
NN_vmaskmovps,           // Conditionally Load Packed Single-Precision Floating-Point Values
NN_vmaxpd,               // Return Maximum Packed Double-Precision Floating-Point Values
NN_vmaxps,               // Packed Single-FP Maximum
NN_vmaxsd,               // Return Maximum Scalar Double-Precision Floating-Point Value
NN_vmaxss,               // Scalar Single-FP Maximum
NN_vminpd,               // Return Minimum Packed Double-Precision Floating-Point Values
NN_vminps,               // Packed Single-FP Minimum
NN_vminsd,               // Return Minimum Scalar Double-Precision Floating-Point Value
NN_vminss,               // Scalar Single-FP Minimum
NN_vmovapd,              // Move Aligned Packed Double-Precision Floating-Point Values
NN_vmovaps,              // Move Aligned Four Packed Single-FP
NN_vmovd,                // Move 32 bits
NN_vmovddup,             // Move One Double-FP and Duplicate
NN_vmovdqa,              // Move Aligned Double Quadword
NN_vmovdqu,              // Move Unaligned Double Quadword
NN_vmovhlps,             // Move High to Low Packed Single-FP
NN_vmovhpd,              // Move High Packed Double-Precision Floating-Point Values
NN_vmovhps,              // Move High Packed Single-FP
NN_vmovlhps,             // Move Low to High Packed Single-FP
NN_vmovlpd,              // Move Low Packed Double-Precision Floating-Point Values
NN_vmovlps,              // Move Low Packed Single-FP
NN_vmovmskpd,            // Extract Packed Double-Precision Floating-Point Sign Mask
NN_vmovmskps,            // Move Mask to Register
NN_vmovntdq,             // Store Double Quadword Using Non-Temporal Hint
NN_vmovntdqa,            // Load Double Quadword Non-Temporal Aligned Hint
NN_vmovntpd,             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
NN_vmovntps,             // Move Aligned Four Packed Single-FP Non Temporal
NN_vmovq,                // Move 64 bits
NN_vmovsd,               // Move Scalar Double-Precision Floating-Point Values
NN_vmovshdup,            // Move Packed Single-FP High and Duplicate
NN_vmovsldup,            // Move Packed Single-FP Low and Duplicate
NN_vmovss,               // Move Scalar Single-FP
NN_vmovupd,              // Move Unaligned Packed Double-Precision Floating-Point Values
NN_vmovups,              // Move Unaligned Four Packed Single-FP
NN_vmpsadbw,             // Compute Multiple Packed Sums of Absolute Difference
NN_vmulpd,               // Multiply Packed Double-Precision Floating-Point Values
NN_vmulps,               // Packed Single-FP Multiply
NN_vmulsd,               // Multiply Scalar Double-Precision Floating-Point Values
NN_vmulss,               // Scalar Single-FP Multiply
NN_vorpd,                // Bitwise Logical OR of Double-Precision Floating-Point Values
NN_vorps,                // Bitwise Logical OR for Single-FP Data
NN_vpabsb,               // Packed Absolute Value Byte
NN_vpabsd,               // Packed Absolute Value Doubleword
NN_vpabsw,               // Packed Absolute Value Word
NN_vpackssdw,            // Pack with Signed Saturation (Dword->Word)
NN_vpacksswb,            // Pack with Signed Saturation (Word->Byte)
NN_vpackusdw,            // Pack with Unsigned Saturation
NN_vpackuswb,            // Pack with Unsigned Saturation (Word->Byte)
NN_vpaddb,               // Packed Add Byte
NN_vpaddd,               // Packed Add Dword
NN_vpaddq,               // Add Packed Quadword Integers
NN_vpaddsb,              // Packed Add with Saturation (Byte)
NN_vpaddsw,              // Packed Add with Saturation (Word)
NN_vpaddusb,             // Packed Add Unsigned with Saturation (Byte)
NN_vpaddusw,             // Packed Add Unsigned with Saturation (Word)
NN_vpaddw,               // Packed Add Word
NN_vpalignr,             // Packed Align Right
NN_vpand,                // Bitwise Logical And
NN_vpandn,               // Bitwise Logical And Not
NN_vpavgb,               // Packed Average (Byte)
NN_vpavgw,               // Packed Average (Word)
NN_vpblendd,             // Blend Packed Dwords
NN_vpblendvb,            // Variable Blend Packed Bytes
NN_vpblendw,             // Blend Packed Words
NN_vpbroadcastb,         // Broadcast a Byte Integer
NN_vpbroadcastd,         // Broadcast a Dword Integer
NN_vpbroadcastq,         // Broadcast a Qword Integer
NN_vpbroadcastw,         // Broadcast a Word Integer
NN_vpclmulqdq,           // Carry-Less Multiplication Quadword
NN_vpcmpeqb,             // Packed Compare for Equal (Byte)
NN_vpcmpeqd,             // Packed Compare for Equal (Dword)
NN_vpcmpeqq,             // Compare Packed Qword Data for Equal
NN_vpcmpeqw,             // Packed Compare for Equal (Word)
NN_vpcmpestri,           // Packed Compare Explicit Length Strings, Return Index
NN_vpcmpestrm,           // Packed Compare Explicit Length Strings, Return Mask
NN_vpcmpgtb,             // Packed Compare for Greater Than (Byte)
NN_vpcmpgtd,             // Packed Compare for Greater Than (Dword)
NN_vpcmpgtq,             // Compare Packed Data for Greater Than
NN_vpcmpgtw,             // Packed Compare for Greater Than (Word)
NN_vpcmpistri,           // Packed Compare Implicit Length Strings, Return Index
NN_vpcmpistrm,           // Packed Compare Implicit Length Strings, Return Mask
NN_vperm2f128,           // Permute Floating-Point Values
NN_vperm2i128,           // Permute Integer Values
NN_vpermd,               // Full Doublewords Element Permutation
NN_vpermilpd,            // Permute Double-Precision Floating-Point Values
NN_vpermilps,            // Permute Single-Precision Floating-Point Values
NN_vpermpd,              // Permute Double-Precision Floating-Point Elements
NN_vpermps,              // Permute Single-Precision Floating-Point Elements
NN_vpermq,               // Qwords Element Permutation
NN_vpextrb,              // Extract Byte
NN_vpextrd,              // Extract Dword
NN_vpextrq,              // Extract Qword
NN_vpextrw,              // Extract Word
NN_vpgatherdd,           // Gather Packed Dword Values Using Signed Dword Indices
NN_vpgatherdq,           // Gather Packed Qword Values Using Signed Dword Indices
NN_vpgatherqd,           // Gather Packed Dword Values Using Signed Qword Indices
NN_vpgatherqq,           // Gather Packed Qword Values Using Signed Qword Indices
NN_vphaddd,              // Packed Horizontal Add Doubleword
NN_vphaddsw,             // Packed Horizontal Add and Saturate
NN_vphaddw,              // Packed Horizontal Add Word
NN_vphminposuw,          // Packed Horizontal Word Minimum
NN_vphsubd,              // Packed Horizontal Subtract Doubleword
NN_vphsubsw,             // Packed Horizontal Subtract and Saturate
NN_vphsubw,              // Packed Horizontal Subtract Word
NN_vpinsrb,              // Insert Byte
NN_vpinsrd,              // Insert Dword
NN_vpinsrq,              // Insert Qword
NN_vpinsrw,              // Insert Word
NN_vpmaddubsw,           // Multiply and Add Packed Signed and Unsigned Bytes
NN_vpmaddwd,             // Packed Multiply and Add
NN_vpmaskmovd,           // Conditionally Store Dword Values Using Mask
NN_vpmaskmovq,           // Conditionally Store Qword Values Using Mask
NN_vpmaxsb,              // Maximum of Packed Signed Byte Integers
NN_vpmaxsd,              // Maximum of Packed Signed Dword Integers
NN_vpmaxsw,              // Packed Signed Integer Word Maximum
NN_vpmaxub,              // Packed Unsigned Integer Byte Maximum
NN_vpmaxud,              // Maximum of Packed Unsigned Dword Integers
NN_vpmaxuw,              // Maximum of Packed Word Integers
NN_vpminsb,              // Minimum of Packed Signed Byte Integers
NN_vpminsd,              // Minimum of Packed Signed Dword Integers
NN_vpminsw,              // Packed Signed Integer Word Minimum
NN_vpminub,              // Packed Unsigned Integer Byte Minimum
NN_vpminud,              // Minimum of Packed Unsigned Dword Integers
NN_vpminuw,              // Minimum of Packed Word Integers
NN_vpmovmskb,            // Move Byte Mask to Integer
NN_vpmovsxbd,            // Packed Move with Sign Extend
NN_vpmovsxbq,            // Packed Move with Sign Extend
NN_vpmovsxbw,            // Packed Move with Sign Extend
NN_vpmovsxdq,            // Packed Move with Sign Extend
NN_vpmovsxwd,            // Packed Move with Sign Extend
NN_vpmovsxwq,            // Packed Move with Sign Extend
NN_vpmovzxbd,            // Packed Move with Zero Extend
NN_vpmovzxbq,            // Packed Move with Zero Extend
NN_vpmovzxbw,            // Packed Move with Zero Extend
NN_vpmovzxdq,            // Packed Move with Zero Extend
NN_vpmovzxwd,            // Packed Move with Zero Extend
NN_vpmovzxwq,            // Packed Move with Zero Extend
NN_vpmuldq,              // Multiply Packed Signed Dword Integers
NN_vpmulhrsw,            // Packed Multiply High with Round and Scale
NN_vpmulhuw,             // Packed Multiply High Unsigned
NN_vpmulhw,              // Packed Multiply High
NN_vpmulld,              // Multiply Packed Signed Dword Integers and Store Low Result
NN_vpmullw,              // Packed Multiply Low
NN_vpmuludq,             // Multiply Packed Unsigned Doubleword Integers
NN_vpor,                 // Bitwise Logical Or
NN_vpsadbw,              // Packed Sum of Absolute Differences
NN_vpshufb,              // Packed Shuffle Bytes
NN_vpshufd,              // Shuffle Packed Doublewords
NN_vpshufhw,             // Shuffle Packed High Words
NN_vpshuflw,             // Shuffle Packed Low Words
NN_vpsignb,              // Packed SIGN Byte
NN_vpsignd,              // Packed SIGN Doubleword
NN_vpsignw,              // Packed SIGN Word
NN_vpslld,               // Packed Shift Left Logical (Dword)
NN_vpslldq,              // Shift Double Quadword Left Logical
NN_vpsllq,               // Packed Shift Left Logical (Qword)
NN_vpsllvd,              // Variable Bit Shift Left Logical (Dword)
NN_vpsllvq,              // Variable Bit Shift Left Logical (Qword)
NN_vpsllw,               // Packed Shift Left Logical (Word)
NN_vpsrad,               // Packed Shift Right Arithmetic (Dword)
NN_vpsravd,              // Variable Bit Shift Right Arithmetic
NN_vpsraw,               // Packed Shift Right Arithmetic (Word)
NN_vpsrld,               // Packed Shift Right Logical (Dword)
NN_vpsrldq,              // Shift Double Quadword Right Logical (Qword)
NN_vpsrlq,               // Packed Shift Right Logical (Qword)
NN_vpsrlvd,              // Variable Bit Shift Right Logical (Dword)
NN_vpsrlvq,              // Variable Bit Shift Right Logical (Qword)
NN_vpsrlw,               // Packed Shift Right Logical (Word)
NN_vpsubb,               // Packed Subtract Byte
NN_vpsubd,               // Packed Subtract Dword
NN_vpsubq,               // Subtract Packed Quadword Integers
NN_vpsubsb,              // Packed Subtract with Saturation (Byte)
NN_vpsubsw,              // Packed Subtract with Saturation (Word)
NN_vpsubusb,             // Packed Subtract Unsigned with Saturation (Byte)
NN_vpsubusw,             // Packed Subtract Unsigned with Saturation (Word)
NN_vpsubw,               // Packed Subtract Word
NN_vptest,               // Logical Compare
NN_vpunpckhbw,           // Unpack High Packed Data (Byte->Word)
NN_vpunpckhdq,           // Unpack High Packed Data (Dword->Qword)
NN_vpunpckhqdq,          // Unpack High Packed Data (Qword->Xmmword)
NN_vpunpckhwd,           // Unpack High Packed Data (Word->Dword)
NN_vpunpcklbw,           // Unpack Low Packed Data (Byte->Word)
NN_vpunpckldq,           // Unpack Low Packed Data (Dword->Qword)
NN_vpunpcklqdq,          // Unpack Low Packed Data (Qword->Xmmword)
NN_vpunpcklwd,           // Unpack Low Packed Data (Word->Dword)
NN_vpxor,                // Bitwise Logical Exclusive Or
NN_vrcpps,               // Packed Single-FP Reciprocal
NN_vrcpss,               // Scalar Single-FP Reciprocal
NN_vroundpd,             // Round Packed Double Precision Floating-Point Values
NN_vroundps,             // Round Packed Single Precision Floating-Point Values
NN_vroundsd,             // Round Scalar Double Precision Floating-Point Values
NN_vroundss,             // Round Scalar Single Precision Floating-Point Values
NN_vrsqrtps,             // Packed Single-FP Square Root Reciprocal
NN_vrsqrtss,             // Scalar Single-FP Square Root Reciprocal
NN_vshufpd,              // Shuffle Packed Double-Precision Floating-Point Values
NN_vshufps,              // Shuffle Single-FP
NN_vsqrtpd,              // Compute Square Roots of Packed Double-Precision Floating-Point Values
NN_vsqrtps,              // Packed Single-FP Square Root
NN_vsqrtsd,              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
NN_vsqrtss,              // Scalar Single-FP Square Root
NN_vstmxcsr,             // Store Streaming SIMD Extensions Technology Control/Status Register
NN_vsubpd,               // Subtract Packed Double-Precision Floating-Point Values
NN_vsubps,               // Packed Single-FP Subtract
NN_vsubsd,               // Subtract Scalar Double-Precision Floating-Point Values
NN_vsubss,               // Scalar Single-FP Subtract
NN_vtestpd,              // Packed Double-Precision Floating-Point Bit Test
NN_vtestps,              // Packed Single-Precision Floating-Point Bit Test
NN_vucomisd,             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
NN_vucomiss,             // Scalar Unordered Single-FP Compare and Set EFLAGS
NN_vunpckhpd,            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
NN_vunpckhps,            // Unpack High Packed Single-FP Data
NN_vunpcklpd,            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
NN_vunpcklps,            // Unpack Low Packed Single-FP Data
NN_vxorpd,               // Bitwise Logical OR of Double-Precision Floating-Point Values
NN_vxorps,               // Bitwise Logical XOR for Single-FP Data
NN_vzeroall,             // Zero All YMM Registers
NN_vzeroupper,           // Zero Upper Bits of YMM Registers
// Transactional Synchronization Extensions
NN_xabort,               // Transaction Abort
NN_xbegin,               // Transaction Begin
NN_xend,                 // Transaction End
NN_xtest,                // Test If In Transactional Execution
// Virtual PC synthetic instructions
NN_vmgetinfo,            // Virtual PC - Get VM Information
NN_vmsetinfo,            // Virtual PC - Set VM Information
NN_vmdxdsbl,             // Virtual PC - Disable Direct Execution
NN_vmdxenbl,             // Virtual PC - Enable Direct Execution
NN_vmcpuid,              // Virtual PC - Virtualized CPU Information
NN_vmhlt,                // Virtual PC - Halt
NN_vmsplaf,              // Virtual PC - Spin Lock Acquisition Failed
NN_vmpushfd,             // Virtual PC - Push virtualized flags register
NN_vmpopfd,              // Virtual PC - Pop virtualized flags register
NN_vmcli,                // Virtual PC - Clear Interrupt Flag
NN_vmsti,                // Virtual PC - Set Interrupt Flag
NN_vmiretd,              // Virtual PC - Return From Interrupt
NN_vmsgdt,               // Virtual PC - Store Global Descriptor Table
NN_vmsidt,               // Virtual PC - Store Interrupt Descriptor Table
NN_vmsldt,               // Virtual PC - Store Local Descriptor Table
NN_vmstr,                // Virtual PC - Store Task Register
NN_vmsdte,               // Virtual PC - Store to Descriptor Table Entry
NN_vpcext,               // Virtual PC - ISA extension
// AMD FMA4
NN_vfmaddsubps,          // Multiply with Alternating Add/Subtract of Packed Single-Precision Floating-Point
NN_vfmaddsubpd,          // Multiply with Alternating Add/Subtract of Packed Double-Precision Floating-Point
NN_vfmsubaddps,          // Multiply with Alternating Subtract/Add of Packed Single-Precision Floating-Point
NN_vfmsubaddpd,          // Multiply with Alternating Subtract/Add of Packed Double-Precision Floating-Point
NN_vfmaddps,             // Multiply and Add Packed Single-Precision Floating-Point
NN_vfmaddpd,             // Multiply and Add Packed Double-Precision Floating-Point
NN_vfmaddss,             // Multiply and Add Scalar Single-Precision Floating-Point
NN_vfmaddsd,             // Multiply and Add Scalar Double-Precision Floating-Point
NN_vfmsubps,             // Multiply and Subtract Packed Single-Precision Floating-Point
NN_vfmsubpd,             // Multiply and Subtract Packed Double-Precision Floating-Point
NN_vfmsubss,             // Multiply and Subtract Scalar Single-Precision Floating-Point
NN_vfmsubsd,             // Multiply and Subtract Scalar Double-Precision Floating-Point
NN_vfnmaddps,            // Negative Multiply and Add Packed Single-Precision Floating-Point
NN_vfnmaddpd,            // Negative Multiply and Add Packed Double-Precision Floating-Point
NN_vfnmaddss,            // Negative Multiply and Add Scalar Single-Precision Floating-Point
NN_vfnmaddsd,            // Negative Multiply and Add Double Single-Precision Floating-Point
NN_vfnmsubps,            // Negative Multiply and Subtract Packed Single-Precision Floating-Point
NN_vfnmsubpd,            // Negative Multiply and Subtract Packed Double-Precision Floating-Point
NN_vfnmsubss,            // Negative Multiply and Subtract Scalar Single-Precision Floating-Point
NN_vfnmsubsd,            // Negative Multiply and Subtract Double Single-Precision Floating-Point
// Intel Memory Protection Extensions (MPX)
NN_bndmk,                // Make Bounds
NN_bndcl,                // Check Lower Bound
NN_bndcu,                // Check Upper Bound
NN_bndcn,                // Check Upper Bound
NN_bndmov,               // Move Bounds
NN_bndldx,               // Load Extended Bounds Using Address Translation
NN_bndstx,               // Store Extended Bounds Using Address Translation
// New xstate instructions
NN_xrstors,              // Restore Processor Extended States Supervisor
NN_xsavec,               // Save Processor Extended States with Compaction
NN_xsaves,               // Save Processor Extended States Supervisor
// PREFETCHWT1 support
NN_prefetchwt1,          // Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
// Memory instructions
NN_clflushopt,           // Flush a Cache Line Optimized
NN_clwb,                 // Cache Line Write Back
NN_pcommit,              // Persistent Commit (deprecated by Intel)
// Protection Key Rights for User Pages
NN_rdpkru,               // Read Protection Key Rights for User Pages
NN_wrpkru,               // Write Data to User Page Key Register
// AVX comparison pseudo-ops
NN_vcmpeqpd,             // Compare Packed Double-Precision Floating-Point Values - Equal (ordered, non-signaling)
NN_vcmpltpd,             // Compare Packed Double-Precision Floating-Point Values - Less-than (ordered, signaling)
NN_vcmplepd,             // Compare Packed Double-Precision Floating-Point Values - Less-than-or-equal (ordered, signaling)
NN_vcmpunordpd,          // Compare Packed Double-Precision Floating-Point Values - Unordered (non-signaling)
NN_vcmpneqpd,            // Compare Packed Double-Precision Floating-Point Values - Not-equal (unordered, non-signaling)
NN_vcmpnltpd,            // Compare Packed Double-Precision Floating-Point Values - Not-less-than (unordered, signaling)
NN_vcmpnlepd,            // Compare Packed Double-Precision Floating-Point Values - Not-less-than-or-equal (unordered, signaling)
NN_vcmpordpd,            // Compare Packed Double-Precision Floating-Point Values - Ordered (non-signaling)
NN_vcmpeq_uqpd,          // Compare Packed Double-Precision Floating-Point Values - Equal (unordered, non-signaling)
NN_vcmpngepd,            // Compare Packed Double-Precision Floating-Point Values - Not-greater-than-or-equal (unordered, signaling)
NN_vcmpngtpd,            // Compare Packed Double-Precision Floating-Point Values - Not-greater-than (unordered, signaling)
NN_vcmpfalsepd,          // Compare Packed Double-Precision Floating-Point Values - False (ordered, non-signaling)
NN_vcmpneq_oqpd,         // Compare Packed Double-Precision Floating-Point Values - Not-equal (ordered, non-signaling)
NN_vcmpgepd,             // Compare Packed Double-Precision Floating-Point Values - Greater-than-or-equal (ordered, signaling)
NN_vcmpgtpd,             // Compare Packed Double-Precision Floating-Point Values - Greater-than (ordered, signaling)
NN_vcmptruepd,           // Compare Packed Double-Precision Floating-Point Values - True (unordered, non-signaling)
NN_vcmpeq_ospd,          // Compare Packed Double-Precision Floating-Point Values - Equal (ordered, signaling)
NN_vcmplt_oqpd,          // Compare Packed Double-Precision Floating-Point Values - Less-than (ordered, non-signaling)
NN_vcmple_oqpd,          // Compare Packed Double-Precision Floating-Point Values - Less-than-or-equal (ordered, non-signaling)
NN_vcmpunord_spd,        // Compare Packed Double-Precision Floating-Point Values - Unordered (signaling)
NN_vcmpneq_uspd,         // Compare Packed Double-Precision Floating-Point Values - Not-equal (unordered, signaling)
NN_vcmpnlt_uqpd,         // Compare Packed Double-Precision Floating-Point Values - Not-less-than (unordered, non-signaling)
NN_vcmpnle_uqpd,         // Compare Packed Double-Precision Floating-Point Values - Not-less-than-or-equal (unordered, non-signaling)
NN_vcmpord_spd,          // Compare Packed Double-Precision Floating-Point Values - Ordered (signaling)
NN_vcmpeq_uspd,          // Compare Packed Double-Precision Floating-Point Values - Equal (unordered, signaling)
NN_vcmpnge_uqpd,         // Compare Packed Double-Precision Floating-Point Values - Not-greater-than-or-equal (unordered, non-signaling)
NN_vcmpngt_uqpd,         // Compare Packed Double-Precision Floating-Point Values - Not-greater-than (unordered, non-signaling)
NN_vcmpfalse_ospd,       // Compare Packed Double-Precision Floating-Point Values - False (ordered, signaling)
NN_vcmpneq_ospd,         // Compare Packed Double-Precision Floating-Point Values - Not-equal (ordered, signaling)
NN_vcmpge_oqpd,          // Compare Packed Double-Precision Floating-Point Values - Greater-than-or-equal (ordered, non-signaling)
NN_vcmpgt_oqpd,          // Compare Packed Double-Precision Floating-Point Values - Greater-than (ordered, non-signaling)
NN_vcmptrue_uspd,        // Compare Packed Double-Precision Floating-Point Values - True (unordered, signaling)
NN_vcmpeqps,             // Packed Single-FP Compare - Equal (ordered, non-signaling)
NN_vcmpltps,             // Packed Single-FP Compare - Less-than (ordered, signaling)
NN_vcmpleps,             // Packed Single-FP Compare - Less-than-or-equal (ordered, signaling)
NN_vcmpunordps,          // Packed Single-FP Compare - Unordered (non-signaling)
NN_vcmpneqps,            // Packed Single-FP Compare - Not-equal (unordered, non-signaling)
NN_vcmpnltps,            // Packed Single-FP Compare - Not-less-than (unordered, signaling)
NN_vcmpnleps,            // Packed Single-FP Compare - Not-less-than-or-equal (unordered, signaling)
NN_vcmpordps,            // Packed Single-FP Compare - Ordered (non-signaling)
NN_vcmpeq_uqps,          // Packed Single-FP Compare - Equal (unordered, non-signaling)
NN_vcmpngeps,            // Packed Single-FP Compare - Not-greater-than-or-equal (unordered, signaling)
NN_vcmpngtps,            // Packed Single-FP Compare - Not-greater-than (unordered, signaling)
NN_vcmpfalseps,          // Packed Single-FP Compare - False (ordered, non-signaling)
NN_vcmpneq_oqps,         // Packed Single-FP Compare - Not-equal (ordered, non-signaling)
NN_vcmpgeps,             // Packed Single-FP Compare - Greater-than-or-equal (ordered, signaling)
NN_vcmpgtps,             // Packed Single-FP Compare - Greater-than (ordered, signaling)
NN_vcmptrueps,           // Packed Single-FP Compare - True (unordered, non-signaling)
NN_vcmpeq_osps,          // Packed Single-FP Compare - Equal (ordered, signaling)
NN_vcmplt_oqps,          // Packed Single-FP Compare - Less-than (ordered, non-signaling)
NN_vcmple_oqps,          // Packed Single-FP Compare - Less-than-or-equal (ordered, non-signaling)
NN_vcmpunord_sps,        // Packed Single-FP Compare - Unordered (signaling)
NN_vcmpneq_usps,         // Packed Single-FP Compare - Not-equal (unordered, signaling)
NN_vcmpnlt_uqps,         // Packed Single-FP Compare - Not-less-than (unordered, non-signaling)
NN_vcmpnle_uqps,         // Packed Single-FP Compare - Not-less-than-or-equal (unordered, non-signaling)
NN_vcmpord_sps,          // Packed Single-FP Compare - Ordered (signaling)
NN_vcmpeq_usps,          // Packed Single-FP Compare - Equal (unordered, signaling)
NN_vcmpnge_uqps,         // Packed Single-FP Compare - Not-greater-than-or-equal (unordered, non-signaling)
NN_vcmpngt_uqps,         // Packed Single-FP Compare - Not-greater-than (unordered, non-signaling)
NN_vcmpfalse_osps,       // Packed Single-FP Compare - False (ordered, signaling)
NN_vcmpneq_osps,         // Packed Single-FP Compare - Not-equal (ordered, signaling)
NN_vcmpge_oqps,          // Packed Single-FP Compare - Greater-than-or-equal (ordered, non-signaling)
NN_vcmpgt_oqps,          // Packed Single-FP Compare - Greater-than (ordered, non-signaling)
NN_vcmptrue_usps,        // Packed Single-FP Compare - True (unordered, signaling)
NN_vcmpeqsd,             // Compare Scalar Double-Precision Floating-Point Values - Equal (ordered, non-signaling)
NN_vcmpltsd,             // Compare Scalar Double-Precision Floating-Point Values - Less-than (ordered, signaling)
NN_vcmplesd,             // Compare Scalar Double-Precision Floating-Point Values - Less-than-or-equal (ordered, signaling)
NN_vcmpunordsd,          // Compare Scalar Double-Precision Floating-Point Values - Unordered (non-signaling)
NN_vcmpneqsd,            // Compare Scalar Double-Precision Floating-Point Values - Not-equal (unordered, non-signaling)
NN_vcmpnltsd,            // Compare Scalar Double-Precision Floating-Point Values - Not-less-than (unordered, signaling)
NN_vcmpnlesd,            // Compare Scalar Double-Precision Floating-Point Values - Not-less-than-or-equal (unordered, signaling)
NN_vcmpordsd,            // Compare Scalar Double-Precision Floating-Point Values - Ordered (non-signaling)
NN_vcmpeq_uqsd,          // Compare Scalar Double-Precision Floating-Point Values - Equal (unordered, non-signaling)
NN_vcmpngesd,            // Compare Scalar Double-Precision Floating-Point Values - Not-greater-than-or-equal (unordered, signaling)
NN_vcmpngtsd,            // Compare Scalar Double-Precision Floating-Point Values - Not-greater-than (unordered, signaling)
NN_vcmpfalsesd,          // Compare Scalar Double-Precision Floating-Point Values - False (ordered, non-signaling)
NN_vcmpneq_oqsd,         // Compare Scalar Double-Precision Floating-Point Values - Not-equal (ordered, non-signaling)
NN_vcmpgesd,             // Compare Scalar Double-Precision Floating-Point Values - Greater-than-or-equal (ordered, signaling)
NN_vcmpgtsd,             // Compare Scalar Double-Precision Floating-Point Values - Greater-than (ordered, signaling)
NN_vcmptruesd,           // Compare Scalar Double-Precision Floating-Point Values - True (unordered, non-signaling)
NN_vcmpeq_ossd,          // Compare Scalar Double-Precision Floating-Point Values - Equal (ordered, signaling)
NN_vcmplt_oqsd,          // Compare Scalar Double-Precision Floating-Point Values - Less-than (ordered, non-signaling)
NN_vcmple_oqsd,          // Compare Scalar Double-Precision Floating-Point Values - Less-than-or-equal (ordered, non-signaling)
NN_vcmpunord_ssd,        // Compare Scalar Double-Precision Floating-Point Values - Unordered (signaling)
NN_vcmpneq_ussd,         // Compare Scalar Double-Precision Floating-Point Values - Not-equal (unordered, signaling)
NN_vcmpnlt_uqsd,         // Compare Scalar Double-Precision Floating-Point Values - Not-less-than (unordered, non-signaling)
NN_vcmpnle_uqsd,         // Compare Scalar Double-Precision Floating-Point Values - Not-less-than-or-equal (unordered, non-signaling)
NN_vcmpord_ssd,          // Compare Scalar Double-Precision Floating-Point Values - Ordered (signaling)
NN_vcmpeq_ussd,          // Compare Scalar Double-Precision Floating-Point Values - Equal (unordered, signaling)
NN_vcmpnge_uqsd,         // Compare Scalar Double-Precision Floating-Point Values - Not-greater-than-or-equal (unordered, non-signaling)
NN_vcmpngt_uqsd,         // Compare Scalar Double-Precision Floating-Point Values - Not-greater-than (unordered, non-signaling)
NN_vcmpfalse_ossd,       // Compare Scalar Double-Precision Floating-Point Values - False (ordered, signaling)
NN_vcmpneq_ossd,         // Compare Scalar Double-Precision Floating-Point Values - Not-equal (ordered, signaling)
NN_vcmpge_oqsd,          // Compare Scalar Double-Precision Floating-Point Values - Greater-than-or-equal (ordered, non-signaling)
NN_vcmpgt_oqsd,          // Compare Scalar Double-Precision Floating-Point Values - Greater-than (ordered, non-signaling)
NN_vcmptrue_ussd,        // Compare Scalar Double-Precision Floating-Point Values - True (unordered, signaling)
NN_vcmpeqss,             // Scalar Single-FP Compare - Equal (ordered, non-signaling)
NN_vcmpltss,             // Scalar Single-FP Compare - Less-than (ordered, signaling)
NN_vcmpless,             // Scalar Single-FP Compare - Less-than-or-equal (ordered, signaling)
NN_vcmpunordss,          // Scalar Single-FP Compare - Unordered (non-signaling)
NN_vcmpneqss,            // Scalar Single-FP Compare - Not-equal (unordered, non-signaling)
NN_vcmpnltss,            // Scalar Single-FP Compare - Not-less-than (unordered, signaling)
NN_vcmpnless,            // Scalar Single-FP Compare - Not-less-than-or-equal (unordered, signaling)
NN_vcmpordss,            // Scalar Single-FP Compare - Ordered (non-signaling)
NN_vcmpeq_uqss,          // Scalar Single-FP Compare - Equal (unordered, non-signaling)
NN_vcmpngess,            // Scalar Single-FP Compare - Not-greater-than-or-equal (unordered, signaling)
NN_vcmpngtss,            // Scalar Single-FP Compare - Not-greater-than (unordered, signaling)
NN_vcmpfalsess,          // Scalar Single-FP Compare - False (ordered, non-signaling)
NN_vcmpneq_oqss,         // Scalar Single-FP Compare - Not-equal (ordered, non-signaling)
NN_vcmpgess,             // Scalar Single-FP Compare - Greater-than-or-equal (ordered, signaling)
NN_vcmpgtss,             // Scalar Single-FP Compare - Greater-than (ordered, signaling)
NN_vcmptruess,           // Scalar Single-FP Compare - True (unordered, non-signaling)
NN_vcmpeq_osss,          // Scalar Single-FP Compare - Equal (ordered, signaling)
NN_vcmplt_oqss,          // Scalar Single-FP Compare - Less-than (ordered, non-signaling)
NN_vcmple_oqss,          // Scalar Single-FP Compare - Less-than-or-equal (ordered, non-signaling)
NN_vcmpunord_sss,        // Scalar Single-FP Compare - Unordered (signaling)
NN_vcmpneq_usss,         // Scalar Single-FP Compare - Not-equal (unordered, signaling)
NN_vcmpnlt_uqss,         // Scalar Single-FP Compare - Not-less-than (unordered, non-signaling)
NN_vcmpnle_uqss,         // Scalar Single-FP Compare - Not-less-than-or-equal (unordered, non-signaling)
NN_vcmpord_sss,          // Scalar Single-FP Compare - Ordered (signaling)
NN_vcmpeq_usss,          // Scalar Single-FP Compare - Equal (unordered, signaling)
NN_vcmpnge_uqss,         // Scalar Single-FP Compare - Not-greater-than-or-equal (unordered, non-signaling)
NN_vcmpngt_uqss,         // Scalar Single-FP Compare - Not-greater-than (unordered, non-signaling)
NN_vcmpfalse_osss,       // Scalar Single-FP Compare - False (ordered, signaling)
NN_vcmpneq_osss,         // Scalar Single-FP Compare - Not-equal (ordered, signaling)
NN_vcmpge_oqss,          // Scalar Single-FP Compare - Greater-than-or-equal (ordered, non-signaling)
NN_vcmpgt_oqss,          // Scalar Single-FP Compare - Greater-than (ordered, non-signaling)
NN_vcmptrue_usss,        // Scalar Single-FP Compare - True (unordered, signaling)
// AVX-512 instructions
NN_valignd,              // Align Doubleword Vectors
NN_valignq,              // Align Quadword Vectors
NN_vblendmpd,            // Blend Float64 Vectors Using an OpMask Control
NN_vblendmps,            // Blend Float32 Vectors Using an OpMask Control
NN_vpblendmb,            // Blend Byte Vectors Using an Opmask Control
NN_vpblendmw,            // Blend Word Vectors Using an Opmask Control
NN_vpblendmd,            // Blend Int32 Vectors Using an OpMask Control
NN_vpblendmq,            // Blend Int64 Vectors Using an OpMask Control
NN_vbroadcastf32x2,      // Load with Broadcast Floating-Point Data
NN_vbroadcastf32x4,      // Load with Broadcast Floating-Point Data
NN_vbroadcastf64x2,      // Load with Broadcast Floating-Point Data
NN_vbroadcastf32x8,      // Load with Broadcast Floating-Point Data
NN_vbroadcastf64x4,      // Load with Broadcast Floating-Point Data
NN_vbroadcasti32x2,      // Load Integer and Broadcast
NN_vbroadcasti32x4,      // Load Integer and Broadcast
NN_vbroadcasti64x2,      // Load Integer and Broadcast
NN_vbroadcasti32x8,      // Load Integer and Broadcast
NN_vbroadcasti64x4,      // Load Integer and Broadcast
NN_vcompresspd,          // Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory
NN_vcompressps,          // Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
NN_vcvtpd2qq,            // Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
NN_vcvtpd2udq,           // Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
NN_vcvtpd2uqq,           // Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
NN_vcvtps2udq,           // Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
NN_vcvtps2qq,            // Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
NN_vcvtps2uqq,           // Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
NN_vcvtqq2pd,            // Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
NN_vcvtqq2ps,            // Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values
NN_vcvtsd2usi,           // Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer
NN_vcvtss2usi,           // Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer
NN_vcvttpd2qq,           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers
NN_vcvttpd2udq,          // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
NN_vcvttpd2uqq,          // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
NN_vcvttps2udq,          // Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
NN_vcvttps2qq,           // Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
NN_vcvttps2uqq,          // Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
NN_vcvttsd2usi,          // Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer
NN_vcvttss2usi,          // Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer
NN_vcvtudq2pd,           // Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values
NN_vcvtudq2ps,           // Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values
NN_vcvtuqq2pd,           // Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values
NN_vcvtuqq2ps,           // Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values
NN_vcvtusi2sd,           // Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
NN_vcvtusi2ss,           // Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
NN_vdbpsadbw,            // Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
NN_vexpandpd,            // Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
NN_vexpandps,            // Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
NN_vextractf32x4,        // Extract Packed Floating-Point Values
NN_vextractf64x2,        // Extract Packed Floating-Point Values
NN_vextractf32x8,        // Extract Packed Floating-Point Values
NN_vextractf64x4,        // Extract Packed Floating-Point Values
NN_vextracti32x4,        // Extract packed Integer Values
NN_vextracti64x2,        // Extract packed Integer Values
NN_vextracti32x8,        // Extract packed Integer Values
NN_vextracti64x4,        // Extract packed Integer Values
NN_vfixupimmpd,          // Fix Up Special Packed Float64 Values
NN_vfixupimmps,          // Fix Up Special Packed Float32 Values
NN_vfixupimmsd,          // Fix Up Special Scalar Float64 Value
NN_vfixupimmss,          // Fix Up Special Scalar Float32 Value
NN_vfpclasspd,           // Tests Types Of a Packed Float64 Values
NN_vfpclassps,           // Tests Types Of a Packed Float32 Values
NN_vfpclasssd,           // Tests Types Of a Scalar Float64 Values
NN_vfpclassss,           // Tests Types Of a Scalar Float32 Values
NN_vgetexppd,            // Convert Exponents of Packed DP FP Values to DP FP Values
NN_vgetexpps,            // Convert Exponents of Packed SP FP Values to SP FP Values
NN_vgetexpsd,            // Convert Exponents of Scalar DP FP Values to DP FP Value
NN_vgetexpss,            // Convert Exponents of Scalar SP FP Values to SP FP Value
NN_vgetmantpd,           // Extract Float64 Vector of Normalized Mantissas from Float64 Vector
NN_vgetmantps,           // Extract Float32 Vector of Normalized Mantissas from Float32 Vector
NN_vgetmantsd,           // Extract Float64 of Normalized Mantissas from Float64 Scalar
NN_vgetmantss,           // Extract Float32 Vector of Normalized Mantissa from Float32 Vector
NN_vinsertf32x4,         // Insert Packed Floating-Point Values
NN_vinsertf64x2,         // Insert Packed Floating-Point Values
NN_vinsertf32x8,         // Insert Packed Floating-Point Values
NN_vinsertf64x4,         // Insert Packed Floating-Point Values
NN_vinserti32x4,         // Insert Packed Integer Values
NN_vinserti64x2,         // Insert Packed Integer Values
NN_vinserti32x8,         // Insert Packed Integer Values
NN_vinserti64x4,         // Insert Packed Integer Values
NN_vmovdqa32,            // Move Aligned Packed Integer Values
NN_vmovdqa64,            // Move Aligned Packed Integer Values
NN_vmovdqu8,             // Move Unaligned Packed Integer Values
NN_vmovdqu16,            // Move Unaligned Packed Integer Values
NN_vmovdqu32,            // Move Unaligned Packed Integer Values
NN_vmovdqu64,            // Move Unaligned Packed Integer Values
NN_vpabsq,               // Packed Absolute Value
NN_vpandd,               // Logical AND
NN_vpandq,               // Logical AND
NN_vpandnd,              // Logical AND NOT
NN_vpandnq,              // Logical AND NOT
NN_vpbroadcastmb2q,      // Broadcast Mask to Vector Register
NN_vpbroadcastmw2d,      // Broadcast Mask to Vector Register
NN_vpcmpb,               // Compare Packed Byte Values Into Mask
NN_vpcmpub,              // Compare Packed Byte Values Into Mask
NN_vpcmpd,               // Compare Packed Integer Values into Mask
NN_vpcmpud,              // Compare Packed Integer Values into Mask
NN_vpcmpq,               // Compare Packed Integer Values into Mask
NN_vpcmpuq,              // Compare Packed Integer Values into Mask
NN_vpcmpw,               // Compare Packed Word Values Into Mask
NN_vpcmpuw,              // Compare Packed Word Values Into Mask
NN_vpcompressd,          // Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
NN_vpcompressq,          // Store Sparse Packed Quadword Integer Values into Dense Memory/Register
NN_vpconflictd,          // Detect Conflicts Within a Vector of Packed Dword Values into Dense Memory/Register
NN_vpconflictq,          // Detect Conflicts Within a Vector of Packed Qword Values into Dense Memory/Register
NN_vpermb,               // Permute Packed Bytes Elements
NN_vpermw,               // Permute Packed Words Elements
NN_vpermi2b,             // Full Permute of Bytes From Two Tables Overwriting the Index
NN_vpermi2w,             // Full Permute From Two Tables Overwriting the Index
NN_vpermi2d,             // Full Permute From Two Tables Overwriting the Index
NN_vpermi2q,             // Full Permute From Two Tables Overwriting the Index
NN_vpermi2ps,            // Full Permute From Two Tables Overwriting the Index
NN_vpermi2pd,            // Full Permute From Two Tables Overwriting the Index
NN_vpermt2b,             // Full Permute of Bytes From Two Tables Overwriting a Table
NN_vpermt2w,             // Full Permute from Two Tables Overwriting one Table
NN_vpermt2d,             // Full Permute from Two Tables Overwriting one Table
NN_vpermt2q,             // Full Permute from Two Tables Overwriting one Table
NN_vpermt2ps,            // Full Permute from Two Tables Overwriting one Table
NN_vpermt2pd,            // Full Permute from Two Tables Overwriting one Table
NN_vpexpandd,            // Load Sparse Packed Doubleword Integer Values from Dense Memory/Register
NN_vpexpandq,            // Load Sparse Packed Quadword Integer Values from Dense Memory/Register
NN_vplzcntd,             // Count the Number of Leading Zero Bits for Packed Dword Values
NN_vplzcntq,             // Count the Number of Leading Zero Bits for Packed Qword Values
NN_vpmadd52luq,          // Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
NN_vpmadd52huq,          // Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators
NN_vpmaxsq,              // Maximum of Packed Signed Integers
NN_vpmaxuq,              // Maximum of Packed Unsigned Integers
NN_vpminsq,              // Minimum of Packed Signed Integers
NN_vpminuq,              // Minimum of Packed Unsigned Integers
NN_vpmovm2b,             // Convert a Mask Register to a Vector Register
NN_vpmovm2w,             // Convert a Mask Register to a Vector Register
NN_vpmovm2d,             // Convert a Mask Register to a Vector Register
NN_vpmovm2q,             // Convert a Mask Register to a Vector Register
NN_vpmovb2m,             // Convert a Vector Register to a Mask
NN_vpmovw2m,             // Convert a Vector Register to a Mask
NN_vpmovd2m,             // Convert a Vector Register to a Mask
NN_vpmovq2m,             // Convert a Vector Register to a Mask
NN_vpmovqb,              // Down Convert QWord to Byte
NN_vpmovsqb,             // Down Convert QWord to Byte
NN_vpmovusqb,            // Down Convert QWord to Byte
NN_vpmovqw,              // Down Convert QWord to Word
NN_vpmovsqw,             // Down Convert QWord to Word
NN_vpmovusqw,            // Down Convert QWord to Word
NN_vpmovqd,              // Down Convert QWord to DWord
NN_vpmovsqd,             // Down Convert QWord to DWord
NN_vpmovusqd,            // Down Convert QWord to DWord
NN_vpmovdb,              // Down Convert DWord to Byte
NN_vpmovsdb,             // Down Convert DWord to Byte
NN_vpmovusdb,            // Down Convert DWord to Byte
NN_vpmovdw,              // Down Convert DWord to Word
NN_vpmovsdw,             // Down Convert DWord to Word
NN_vpmovusdw,            // Down Convert DWord to Word
NN_vpmovwb,              // Down Convert Word to Byte
NN_vpmovswb,             // Down Convert Word to Byte
NN_vpmovuswb,            // Down Convert Word to Byte
NN_vpmullq,              // Multiply Packed Integers and Store Low Result
NN_vpmultishiftqb,       // Select Packed Unaligned Bytes from Quadword Sources
NN_vpord,                // Bitwise Logical Or
NN_vporq,                // Bitwise Logical Or
NN_vprold,               // Bit Rotate Left
NN_vprolvd,              // Bit Rotate Left
NN_vprolq,               // Bit Rotate Left
NN_vprolvq,              // Bit Rotate Left
NN_vprord,               // Bit Rotate Right
NN_vprorvd,              // Bit Rotate Right
NN_vprorq,               // Bit Rotate Right
NN_vprorvq,              // Bit Rotate Right
NN_vpscatterdd,          // Scatter Packed Dword with Signed Dword
NN_vpscatterdq,          // Scatter Packed Qword with Signed Qword Indices
NN_vpscatterqd,          // Scatter Packed Dword with Signed Dword
NN_vpscatterqq,          // Scatter Packed Qword with Signed Qword Indices
NN_vpsraq,               // Bit Shift Arithmetic Right
NN_vpsllvw,              // Variable Bit Shift Left Logical
NN_vpsrlvw,              // Variable Bit Shift Right Logical
NN_vptestnmb,            // Logical NAND and Set
NN_vptestnmw,            // Logical NAND and Set
NN_vptestnmd,            // Logical NAND and Set
NN_vptestnmq,            // Logical NAND and Set
NN_vshuff32x4,           // Shuffle Packed Values at 128-bit Granularity
NN_vshuff64x2,           // Shuffle Packed Values at 128-bit Granularity
NN_vshufi32x4,           // Shuffle Packed Values at 128-bit Granularity
NN_vshufi64x2,           // Shuffle Packed Values at 128-bit Granularity
NN_vpternlogd,           // Bitwise Ternary Logic
NN_vpternlogq,           // Bitwise Ternary Logic
NN_vptestmb,             // Logical AND and Set Mask
NN_vptestmw,             // Logical AND and Set Mask
NN_vptestmd,             // Logical AND and Set Mask
NN_vptestmq,             // Logical AND and Set Mask
NN_vpsravw,              // Variable Bit Shift Right Arithmetic
NN_vpsravq,              // Variable Bit Shift Right Arithmetic
NN_vpxord,               // Exclusive Or
NN_vpxorq,               // Exclusive Or
NN_vrangepd,             // Range Restriction Calculation For Packed Pairs of Float64 Values
NN_vrangeps,             // Range Restriction Calculation For Packed Pairs of Float32 Values
NN_vrangesd,             // Range Restriction Calculation From a pair of Scalar Float64 Values
NN_vrangess,             // Range Restriction Calculation From a Pair of Scalar Float32 Values
NN_vrcp14pd,             // Compute Approximate Reciprocals of Packed Float64 Values
NN_vrcp14sd,             // Compute Approximate Reciprocal of Scalar Float64 Value
NN_vrcp14ps,             // Compute Approximate Reciprocals of Packed Float32 Values
NN_vrcp14ss,             // Compute Approximate Reciprocal of Scalar Float32 Value
NN_vreducepd,            // Perform Reduction Transformation on Packed Float64 Values
NN_vreducesd,            // Perform a Reduction Transformation on a Scalar Float64 Value
NN_vreduceps,            // Perform Reduction Transformation on Packed Float32 Values
NN_vreducess,            // Perform a Reduction Transformation on a Scalar Float32 Value
NN_vrndscalepd,          // Round Packed Float64 Values To Include A Given Number Of Fraction Bits
NN_vrndscalesd,          // Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
NN_vrndscaleps,          // Round Packed Float32 Values To Include A Given Number Of Fraction Bits
NN_vrndscaless,          // Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
NN_vrsqrt14pd,           // Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
NN_vrsqrt14sd,           // Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
NN_vrsqrt14ps,           // Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
NN_vrsqrt14ss,           // Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
NN_vscalefpd,            // Scale Packed Float64 Values With Float64 Values
NN_vscalefsd,            // Scale Scalar Float64 Values With Float64 Values
NN_vscalefps,            // Scale Packed Float32 Values With Float32 Values
NN_vscalefss,            // Scale Scalar Float32 Value With Float32 Value
NN_vscatterdps,          // Scatter Packed Single, Packed Double with Signed Dword and Qword Indices
NN_vscatterdpd,          // Scatter Packed Single, Packed Double with Signed Dword and Qword Indices
NN_vscatterqps,          // Scatter Packed Single, Packed Double with Signed Dword and Qword Indices
NN_vscatterqpd,          // Scatter Packed Single, Packed Double with Signed Dword and Qword Indices
NN_vexp2pd,              // Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error
NN_vexp2ps,              // Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error
NN_vrcp28pd,             // Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
NN_vrcp28sd,             // Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
NN_vrcp28ps,             // Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
NN_vrcp28ss,             // Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
NN_vrsqrt28pd,           // Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
NN_vrsqrt28sd,           // Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
NN_vrsqrt28ps,           // Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
NN_vrsqrt28ss,           // Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
NN_vgatherpf0dps,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
NN_vgatherpf0qps,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
NN_vgatherpf0dpd,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
NN_vgatherpf0qpd,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
NN_vgatherpf1dps,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
NN_vgatherpf1qps,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
NN_vgatherpf1dpd,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
NN_vgatherpf1qpd,        // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
NN_vscatterpf0dps,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
NN_vscatterpf0qps,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
NN_vscatterpf0dpd,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
NN_vscatterpf0qpd,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
NN_vscatterpf1dps,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
NN_vscatterpf1qps,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
NN_vscatterpf1dpd,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
NN_vscatterpf1qpd,       // Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
// AVX-512 comparison pseudo-ops
NN_vpcmpltd,             // Compare Packed Integer Values into Mask
NN_vpcmpled,             // Compare Packed Integer Values into Mask
NN_vpcmpneqd,            // Compare Packed Integer Values into Mask
NN_vpcmpnltd,            // Compare Packed Integer Values into Mask
NN_vpcmpnled,            // Compare Packed Integer Values into Mask
NN_vpcmpequd,            // Compare Packed Integer Values into Mask
NN_vpcmpltud,            // Compare Packed Integer Values into Mask
NN_vpcmpleud,            // Compare Packed Integer Values into Mask
NN_vpcmpnequd,           // Compare Packed Integer Values into Mask
NN_vpcmpnltud,           // Compare Packed Integer Values into Mask
NN_vpcmpnleud,           // Compare Packed Integer Values into Mask
NN_vpcmpltq,             // Compare Packed Integer Values into Mask
NN_vpcmpleq,             // Compare Packed Integer Values into Mask
NN_vpcmpneqq,            // Compare Packed Integer Values into Mask
NN_vpcmpnltq,            // Compare Packed Integer Values into Mask
NN_vpcmpnleq,            // Compare Packed Integer Values into Mask
NN_vpcmpequq,            // Compare Packed Integer Values into Mask
NN_vpcmpltuq,            // Compare Packed Integer Values into Mask
NN_vpcmpleuq,            // Compare Packed Integer Values into Mask
NN_vpcmpnequq,           // Compare Packed Integer Values into Mask
NN_vpcmpnltuq,           // Compare Packed Integer Values into Mask
NN_vpcmpnleuq,           // Compare Packed Integer Values into Mask
// Opmask instructions
NN_kaddw,                // ADD Two Masks
NN_kaddb,                // ADD Two Masks
NN_kaddq,                // ADD Two Masks
NN_kaddd,                // ADD Two Masks
NN_kandw,                // Bitwise Logical AND Masks
NN_kandb,                // Bitwise Logical AND Masks
NN_kandq,                // Bitwise Logical AND Masks
NN_kandd,                // Bitwise Logical AND Masks
NN_kandnw,               // Bitwise Logical AND NOT Masks
NN_kandnb,               // Bitwise Logical AND NOT Masks
NN_kandnq,               // Bitwise Logical AND NOT Masks
NN_kandnd,               // Bitwise Logical AND NOT Masks
NN_kmovw,                // Move from and to Mask Registers
NN_kmovb,                // Move from and to Mask Registers
NN_kmovq,                // Move from and to Mask Registers
NN_kmovd,                // Move from and to Mask Registers
NN_kunpckbw,             // Unpack for Mask Registers
NN_kunpckwd,             // Unpack for Mask Registers
NN_kunpckdq,             // Unpack for Mask Registers
NN_knotw,                // NOT Mask Register
NN_knotb,                // NOT Mask Register
NN_knotq,                // NOT Mask Register
NN_knotd,                // NOT Mask Register
NN_korw,                 // Bitwise Logical OR Masks
NN_korb,                 // Bitwise Logical OR Masks
NN_korq,                 // Bitwise Logical OR Masks
NN_kord,                 // Bitwise Logical OR Masks
NN_kortestw,             // OR Masks And Set Flags
NN_kortestb,             // OR Masks And Set Flags
NN_kortestq,             // OR Masks And Set Flags
NN_kortestd,             // OR Masks And Set Flags
NN_kshiftlw,             // Shift Left Mask Registers
NN_kshiftlb,             // Shift Left Mask Registers
NN_kshiftlq,             // Shift Left Mask Registers
NN_kshiftld,             // Shift Left Mask Registers
NN_kshiftrw,             // Shift Right Mask Registers
NN_kshiftrb,             // Shift Right Mask Registers
NN_kshiftrq,             // Shift Right Mask Registers
NN_kshiftrd,             // Shift Right Mask Registers
NN_kxnorw,               // Bitwise Logical XNOR Masks
NN_kxnorb,               // Bitwise Logical XNOR Masks
NN_kxnorq,               // Bitwise Logical XNOR Masks
NN_kxnord,               // Bitwise Logical XNOR Masks
NN_ktestw,               // Packed Bit Test Masks and Set Flags
NN_ktestb,               // Packed Bit Test Masks and Set Flags
NN_ktestq,               // Packed Bit Test Masks and Set Flags
NN_ktestd,               // Packed Bit Test Masks and Set Flags
NN_kxorw,                // Bitwise Logical XOR Masks
NN_kxorb,                // Bitwise Logical XOR Masks
NN_kxorq,                // Bitwise Logical XOR Masks
NN_kxord,                // Bitwise Logical XOR Masks
// SHA Extensions
NN_sha1rnds4,            // Perform Four Rounds of SHA1 Operation
NN_sha1nexte,            // Calculate SHA1 State Variable E after Four Rounds
NN_sha1msg1,             // Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
NN_sha1msg2,             // Perform a Final Calculation for the Next Four SHA1 Message Dwords
NN_sha256rnds2,          // Perform Two Rounds of SHA256 Operation
NN_sha256msg1,           // Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords
NN_sha256msg2,           // Perform a Final Calculation for the Next Four SHA256 Message Dwords
// Intel Software Guard Extensions
NN_encls,                // Execute an Enclave System Function of Specified Leaf Number
NN_enclu,                // Execute an Enclave User Function of Specified Leaf Number
// AMD XOP
NN_vfrczpd,              // Extract Fraction Packed Double-Precision Floating-Point
NN_vfrczps,              // Extract Fraction Packed Single-Precision Floating-Point
NN_vfrczsd,              // Extract Fraction Scalar Double-Precision Floating-Point
NN_vfrczss,              // Extract Fraction Scalar Single-Precision Floating Point
NN_vpcmov,               // Vector Conditional Moves
NN_vpcomb,               // Compare Vector Signed Bytes
NN_vpcomd,               // Compare Vector Signed Doublewords
NN_vpcomq,               // Compare Vector Signed Quadwords
NN_vpcomub,              // Compare Vector Unsigned Bytes
NN_vpcomud,              // Compare Vector Unsigned Doublewords
NN_vpcomuq,              // Compare Vector Unsigned Quadwords
NN_vpcomuw,              // Compare Vector Unsigned Words
NN_vpcomw,               // Compare Vector Signed Words
NN_vpermil2pd,           // Permute Two-Source Double-Precision Floating-Point Values
NN_vpermil2ps,           // Permute Two-Source Single-Precision Floating-Point Values
NN_vphaddbd,             // Packed Horizontal Add Signed Byte to Signed Doubleword
NN_vphaddbq,             // Packed Horizontal Add Signed Byte to Signed Quadword
NN_vphaddbw,             // Packed Horizontal Add Signed Byte to Signed Word
NN_vphadddq,             // Packed Horizontal Add Signed Doubleword to Signed Quadword
NN_vphaddubd,            // Packed Horizontal Add Unsigned Byte to Doubleword
NN_vphaddubq,            // Packed Horizontal Add Unsigned Byte to Quadword
NN_vphaddubw,            // Packed Horizontal Add Unsigned Byte to Word
NN_vphaddudq,            // Packed Horizontal Add Unsigned Doubleword to Quadword
NN_vphadduwd,            // Packed Horizontal Add Unsigned Word to Doubleword
NN_vphadduwq,            // Packed Horizontal Add Unsigned Word to Quadword
NN_vphaddwd,             // Packed Horizontal Add Signed Word to Signed Doubleword
NN_vphaddwq,             // Packed Horizontal Add Signed Word to Signed Quadword
NN_vphsubbw,             // Packed Horizontal Subtract Signed Byte to Signed Word
NN_vphsubdq,             // Packed Horizontal Subtract Signed Doubleword to Signed Quadword
NN_vphsubwd,             // Packed Horizontal Subtract Signed Word to Signed Doubleword
NN_vpmacsdd,             // Packed Multiply Accumulate Signed Doubleword to Signed Doubleword
NN_vpmacsdqh,            // Packed Multiply Accumulate Signed High Doubleword to Signed Quadword
NN_vpmacsdql,            // Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword
NN_vpmacssdd,            // Packed Multiply Accumulate Signed Doubleword to Signed Doubleword with Saturation
NN_vpmacssdqh,           // Packed Multiply Accumulate Signed High Doubleword to Signed Quadword with Saturation
NN_vpmacssdql,           // Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword with Saturation
NN_vpmacsswd,            // Packed Multiply Accumulate Signed Word to Signed Doubleword with Saturation
NN_vpmacssww,            // Packed Multiply Accumulate Signed Word to Signed Word with Saturation
NN_vpmacswd,             // Packed Multiply Accumulate Signed Word to Signed Doubleword
NN_vpmacsww,             // Packed Multiply Accumulate Signed Word to Signed Word
NN_vpmadcsswd,           // Packed Multiply, Add and Accumulate Signed Word to Signed Doubleword with Saturation
NN_vpmadcswd,            // Packed Multiply Add and Accumulate Signed Word to Signed Doubleword
NN_vpperm,               // Packed Permute Bytes
NN_vprotb,               // Packed Rotate Bytes
NN_vprotd,               // Packed Rotate Doublewords
NN_vprotq,               // Packed Rotate Quadwords
NN_vprotw,               // Packed Rotate Words
NN_vpshab,               // Packed Shift Arithmetic Bytes
NN_vpshad,               // Packed Shift Arithmetic Doublewords
NN_vpshaq,               // Packed Shift Arithmetic Quadwords
NN_vpshaw,               // Packed Shift Arithmetic Words
NN_vpshlb,               // Packed Shift Logical Bytes
NN_vpshld,               // Packed Shift Logical Doublewords
NN_vpshlq,               // Packed Shift Logical Quadwords
NN_vpshlw,               // Packed Shift Logical Words
// AMD XOP comparison pseudo-ops
NN_vpcomltb,             // Compare Vector Signed Bytes
NN_vpcomleb,             // Compare Vector Signed Bytes
NN_vpcomgtb,             // Compare Vector Signed Bytes
NN_vpcomgeb,             // Compare Vector Signed Bytes
NN_vpcomeqb,             // Compare Vector Signed Bytes
NN_vpcomneqb,            // Compare Vector Signed Bytes
NN_vpcomfalseb,          // Compare Vector Signed Bytes
NN_vpcomtrueb,           // Compare Vector Signed Bytes
NN_vpcomltw,             // Compare Vector Signed Words
NN_vpcomlew,             // Compare Vector Signed Words
NN_vpcomgtw,             // Compare Vector Signed Words
NN_vpcomgew,             // Compare Vector Signed Words
NN_vpcomeqw,             // Compare Vector Signed Words
NN_vpcomneqw,            // Compare Vector Signed Words
NN_vpcomfalsew,          // Compare Vector Signed Words
NN_vpcomtruew,           // Compare Vector Signed Words
NN_vpcomltd,             // Compare Vector Signed Doublewords
NN_vpcomled,             // Compare Vector Signed Doublewords
NN_vpcomgtd,             // Compare Vector Signed Doublewords
NN_vpcomged,             // Compare Vector Signed Doublewords
NN_vpcomeqd,             // Compare Vector Signed Doublewords
NN_vpcomneqd,            // Compare Vector Signed Doublewords
NN_vpcomfalsed,          // Compare Vector Signed Doublewords
NN_vpcomtrued,           // Compare Vector Signed Doublewords
NN_vpcomltq,             // Compare Vector Signed Quadwords
NN_vpcomleq,             // Compare Vector Signed Quadwords
NN_vpcomgtq,             // Compare Vector Signed Quadwords
NN_vpcomgeq,             // Compare Vector Signed Quadwords
NN_vpcomeqq,             // Compare Vector Signed Quadwords
NN_vpcomneqq,            // Compare Vector Signed Quadwords
NN_vpcomfalseq,          // Compare Vector Signed Quadwords
NN_vpcomtrueq,           // Compare Vector Signed Quadwords
NN_vpcomltub,            // Compare Vector Unsigned Bytes
NN_vpcomleub,            // Compare Vector Unsigned Bytes
NN_vpcomgtub,            // Compare Vector Unsigned Bytes
NN_vpcomgeub,            // Compare Vector Unsigned Bytes
NN_vpcomequb,            // Compare Vector Unsigned Bytes
NN_vpcomnequb,           // Compare Vector Unsigned Bytes
NN_vpcomfalseub,         // Compare Vector Unsigned Bytes
NN_vpcomtrueub,          // Compare Vector Unsigned Bytes
NN_vpcomltuw,            // Compare Vector Unsigned Words
NN_vpcomleuw,            // Compare Vector Unsigned Words
NN_vpcomgtuw,            // Compare Vector Unsigned Words
NN_vpcomgeuw,            // Compare Vector Unsigned Words
NN_vpcomequw,            // Compare Vector Unsigned Words
NN_vpcomnequw,           // Compare Vector Unsigned Words
NN_vpcomfalseuw,         // Compare Vector Unsigned Words
NN_vpcomtrueuw,          // Compare Vector Unsigned Words
NN_vpcomltud,            // Compare Vector Unsigned Doublewords
NN_vpcomleud,            // Compare Vector Unsigned Doublewords
NN_vpcomgtud,            // Compare Vector Unsigned Doublewords
NN_vpcomgeud,            // Compare Vector Unsigned Doublewords
NN_vpcomequd,            // Compare Vector Unsigned Doublewords
NN_vpcomnequd,           // Compare Vector Unsigned Doublewords
NN_vpcomfalseud,         // Compare Vector Unsigned Doublewords
NN_vpcomtrueud,          // Compare Vector Unsigned Doublewords
NN_vpcomltuq,            // Compare Vector Unsigned Quadwords
NN_vpcomleuq,            // Compare Vector Unsigned Quadwords
NN_vpcomgtuq,            // Compare Vector Unsigned Quadwords
NN_vpcomgeuq,            // Compare Vector Unsigned Quadwords
NN_vpcomequq,            // Compare Vector Unsigned Quadwords
NN_vpcomnequq,           // Compare Vector Unsigned Quadwords
NN_vpcomfalseuq,         // Compare Vector Unsigned Quadwords
NN_vpcomtrueuq,          // Compare Vector Unsigned Quadwords
// AMD Excavator
NN_monitorx,             // Setup Monitor Address
NN_mwaitx,               // Monitor Wait with Timeout
// AMD Zen
NN_clzero,               // Zero out 64 byte cache
// Intel Processor Trace
NN_ptwrite,              // Write Data to a Processor Trace Packet
// new Intel AVX-512 instructions (December 2016)
NN_v4fmaddps,            // Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
NN_v4fnmaddps,           // Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
NN_v4fmaddss,            // Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
NN_v4fnmaddss,           // Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
NN_vp4dpwssd,            // Dot Product of Signed Words with Dword Accumulation (4-iterations)
NN_vp4dpwssds,           // Dot Product of Signed Words with Dword Accumulation and Saturation (4-iterations)
NN_vpopcntd,             // Return the Count of Number of Bits Set to 1 in DWORD
NN_vpopcntq,             // Return the Count of Number of Bits Set to 1 in QWORD
// Read Processor ID
NN_rdpid,                // Read Processor ID
// Invoke VM function
NN_vmfunc,               // Invoke VM function
// Control-flow Enforcement
NN_incsspd,              // Increment Shadow Stack Pointer (by 4)
NN_incsspq,              // Increment Shadow Stack Pointer (by 8)
NN_rdsspd,               // Read (low 32 bits of) Shadow Stack Pointer
NN_rdsspq,               // Read Shadow Stack Pointer
NN_saveprevssp,          // Save Previous Shadow Stack Pointer
NN_rstorssp,             // Restore saved Shadow Stack Pointer
NN_wrssd,                // Write (4 bytes) to shadow stack
NN_wrssq,                // Write (8 bytes) to shadow stack
NN_wrussd,               // Write (4 bytes) to User Shadow Stack
NN_wrussq,               // Write (8 bytes) to User Shadow Stack
NN_setssbsy,             // Mark Shadow Stack Busy
NN_clrssbsy,             // Clear Shadow Stack Busy Flag
NN_endbr64,              // Terminate an Indirect Branch in 64-bit Mode
NN_endbr32,              // Terminate an Indirect Branch in 32-bit and Compatibility Mode
// Undefined Instruction
NN_ud0,                 // Undefined Instruction
NN_ud1,                 // Undefined Instruction
// Enqueue Stores
NN_enqcmd,              // Enqueue Command
NN_enqcmds,             // Enqueue Command Supervisor
// AMD Zen2
NN_mcommit,             // Commit Stores to Memory
NN_rdpru,               // Read Processor Register
// Intel Tremont instructions
NN_cldemote,            // Cache Line Demote
NN_enclv,               // Execute an Enclave VMM Function of Specified Leaf Number
// Direct Stores
NN_movdiri,             // Move Doubleword as Direct Store
NN_movdir64b,           // Move 64 Bytes as Direct Store
// Intel WAITPKG instructions
NN_tpause,              // Timed PAUSE
NN_umonitor,            // User Level Set Up Monitor Address
NN_umwait,              // User Level Monitor Wait
// Intel Sapphire Rapids instructions
NN_serialize,           // Serialize Instruction Execution
// Intel TSX
NN_xresldtrk,           // Resume Tracking Load Addresses
NN_xsusldtrk,           // Suspend Tracking Load Addresses
// Intel Affine Transformation instructions
NN_gf2p8mulb,           // Galois Field Multiply Bytes
NN_gf2p8affineqb,       // Computes Affine Transformation
NN_gf2p8affineinvqb,    // Computes Inverse Affine Transformation
// VEX versions
NN_vgf2p8mulb,          // Galois Field Multiply Bytes
NN_vgf2p8affineqb,      // Computes Affine Transformation
NN_vgf2p8affineinvqb,   // Computes Inverse Affine Transformation
// Intrinsics for Saving and Restoring the Extended Processor States (64-bits)
NN_fxsave64,            // Fast save FP context (64-bits)
NN_fxrstor64,           // Fast restore FP context (64-bits)
// AVX-VNNI
NN_vpdpbusd,            // Multiply and Add Unsigned and Signed Bytes
NN_vpdpbusds,           // Multiply and Add Unsigned and Signed Bytes With Saturation
NN_vpdpwssd,            // Multiply and Add Signed Word Integers
NN_vpdpwssds,           // Multiply and Add Signed Word Integers With Saturation
// AVX512-VBMI2
NN_vpcompressb,        // Store Sparse Packed Byte Integer Values Into Dense Memory/Register
NN_vpcompressw,        // Store Sparse Packed Word Integer Values Into Dense Memory/Register
NN_vpexpandb,          // Expand Byte Values
NN_vpexpandw,          // Expand Word Values
NN_vpshldw,            // Concatenate and Shift Packed Data Left Logical
NN_vpshldd,            // Concatenate and Shift Packed Data Left Logical
NN_vpshldq,            // Concatenate and Shift Packed Data Left Logical
NN_vpshldvw,           // Concatenate and Variable Shift Packed Data Left Logical
NN_vpshldvd,           // Concatenate and Variable Shift Packed Data Left Logical
NN_vpshldvq,           // Concatenate and Variable Shift Packed Data Left Logical
NN_vpshrdw,            // Concatenate and Shift Packed Data Right Logical
NN_vpshrdd,            // Concatenate and Shift Packed Data Right Logical
NN_vpshrdq,            // Concatenate and Shift Packed Data Right Logical
NN_vpshrdvw,           // Concatenate and Variable Shift Packed Data Right Logical
NN_vpshrdvd,           // Concatenate and Variable Shift Packed Data Right Logical
NN_vpshrdvq,           // Concatenate and Variable Shift Packed Data Right Logical
// AVX512-BITALG
NN_vpopcntb,           // Return the Count of Number of Bits Set to 1 in BYTE
NN_vpopcntw,           // Return the Count of Number of Bits Set to 1 in WORD
NN_vpshufbitqmb,       // Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
// AVX512-VP2INTERSECT
NN_vp2intersectd,     // Compute Intersection Between DWORDS to aPair of Mask Registers
NN_vp2intersectq,     // Compute Intersection Between QUADWORDS to aPair of Mask Registers
// AVX512-BF16
NN_vcvtne2ps2bf16,    // Convert Two Packed Single Data to One Packed BF16 Data
NN_vcvtneps2bf16,     // Convert Packed Single Data to Packed BF16 Data
NN_vdpbf16ps,         // Dot Product of BF16 Pairs Accumulated Into Packed Single Precision
// AVX512-FP16
NN_vaddph,            // Add Packed FP16 Values
NN_vcmpph,            // Compare Packed FP16 Values
NN_vcvtdq2ph,         // Convert Packed Signed Doubleword Integers to Packed FP16 Values
NN_vcvtpd2ph,         // Convert Packed Double Precision FP Values to Packed FP16 Values
NN_vcvtph2dq,         // Convert Packed FP16 Values to Signed Doubleword Integers
NN_vcvtph2pd,         // Convert Packed FP16 Values to FP64 Values
NN_vcvtph2psx,        // Convert Packed FP16 Values to Single Precision Floating-Point Values
NN_vcvtph2qq,         // Convert Packed FP16 Values to Signed Quadword Integer Values
NN_vcvtph2udq,        // Convert Packed FP16 Values to Unsigned Doubleword Integers
NN_vcvtph2uqq,        // Convert Packed FP16 Values to Unsigned Quadword Integers
NN_vcvtph2uw,         // Convert Packed FP16 Values to Unsigned Word Integers
NN_vcvtph2w,          // Convert Packed FP16 Values to Signed Word Integers
NN_vcvtps2phx,        // Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
NN_vcvtqq2ph,         // Convert Packed Signed Quadword Integers to Packed FP16 Values
NN_vcvttph2dq,        // Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
NN_vcvttph2qq,        // Convert with Truncation Packed FP16 Values to Signed Quadword Integers
NN_vcvttph2udq,       // Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers
NN_vcvttph2uqq,       // Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
NN_vcvttph2uw,        // Convert Packed FP16 Values to Unsigned Word Integers
NN_vcvttph2w,         // Convert Packed FP16 Values to Signed Word Integers
NN_vcvtudq2ph,        // Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
NN_vcvtuqq2ph,        // Convert Packed Unsigned Quadword Integers to Packed FP16 Values
NN_vcvtuw2ph,         // Convert Packed Unsigned Word Integers to FP16 Values
NN_vcvtw2ph,          // Convert Packed Signed Word Integers to FP16 Values
NN_vdivph,            // Divide Packed FP16 Values
NN_vfcmaddcph,        // Complex Multiply and Accumulate FP16 Values
NN_vfcmulcph,         // Complex Multiply FP16 Values
NN_vfmadd132ph,       // Fused Multiply-Add of Packed FP16 Values
NN_vfmadd213ph,       // Fused Multiply-Add of Packed FP16 Values
NN_vfmadd231ph,       // Fused Multiply-Add of Packed FP16 Values
NN_vfmaddcph,         // Complex Multiply and Accumulate FP16 Values
NN_vfmaddsub132ph,    // Fused Multiply-Alternating Add/Subtract of Packed FP16 Values
NN_vfmaddsub213ph,    // Fused Multiply-Alternating Add/Subtract of Packed FP16 Values
NN_vfmaddsub231ph,    // Fused Multiply-Alternating Add/Subtract of Packed FP16 Values
NN_vfmsub132ph,       // Fused Multiply-Subtract of Packed FP16 Values
NN_vfmsub213ph,       // Fused Multiply-Subtract of Packed FP16 Values
NN_vfmsub231ph,       // Fused Multiply-Subtract of Packed FP16 Values
NN_vfmsubadd132ph,    // Fused Multiply-Alternating Subtract/Add of Packed FP16 Values
NN_vfmsubadd213ph,    // Fused Multiply-Alternating Subtract/Add of Packed FP16 Values
NN_vfmsubadd231ph,    // Fused Multiply-Alternating Subtract/Add of Packed FP16 Values
NN_vfmulcph,          // Complex Multiply FP16 Values
NN_vfnmadd132ph,      // Fused Multiply-Add of Packed FP16 Values
NN_vfnmadd213ph,      // Fused Multiply-Add of Packed FP16 Values
NN_vfnmadd231ph,      // Fused Multiply-Add of Packed FP16 Values
NN_vfnmsub132ph,      // Fused Multiply-Subtract of Packed FP16 Values
NN_vfnmsub213ph,      // Fused Multiply-Subtract of Packed FP16 Values
NN_vfnmsub231ph,      // Fused Multiply-Subtract of Packed FP16 Values
NN_vfpclassph,        // Test Types of Packed FP16 Values
NN_vgetexpph,         // Fused Multiply-Subtract of Packed FP16 Values
NN_vgetmantph,        // Extract FP16 Vector of Normalized Mantissas from FP16 Vector
NN_vmaxph,            // Return Maximum of Packed FP16 Values
NN_vminph,            // Return Minimum of Packed FP16 Values
NN_vmulph,            // Multiply Packed FP16 Values
NN_vrcpph,            // Compute Reciprocals of Packed FP16 Values
NN_vreduceph,         // Perform Reduction Transformation on Packed FP16 Values
NN_vrndscaleph,       // Round Packed FP16 Values to Include a Given Number of Fraction Bits
NN_vrsqrtph,          // Compute Reciprocals of Square Roots of Packed FP16 Values
NN_vscalefph,         // Scale Packed FP16 Values with FP16 Values
NN_vsqrtph,           // Compute Square Root of Packed FP16 Values
NN_vsubph,            // Subtract Packed FP16 Values
// AVX512-FP16-128N
NN_vmovw,             // Move Word
// AVX512-FP16-SCALAR
NN_vaddsh,            // Add Scalar FP16 Values
NN_vcmpsh,            // Compare Scalar FP16 Values
NN_vcomish,           // Compare Scalar Ordered FP16 Values and Set EFLAGS
NN_vcvtsd2sh,         // Convert Low FP64 Value to an FP16 Value
NN_vcvtsh2sd,         // Convert Low FP16 Value to an FP64 Value
NN_vcvtsh2si,         // Convert Low FP16 Value to Signed Integer
NN_vcvtsh2ss,         // Convert Low FP16 Value to FP32 Value
NN_vcvtsh2usi,        // Convert Low FP16 Value to Unsigned Integer
NN_vcvtsi2sh,         // Convert a Signed Doubleword/Quadword Integer to an FP16 Value
NN_vcvtss2sh,         // Convert Low FP32 Value to an FP16 Value
NN_vcvttsh2si,        // Convert with Truncation Low FP16 Value to a Signed Integer
NN_vcvttsh2usi,       // Convert with Truncation Low FP16 Value to an Unsigned Integer
NN_vcvtusi2sh,        // Convert Unsigned Doubleword Integer to an FP16 Value
NN_vdivsh,            // Divide Scalar FP16 Values
NN_vfcmaddcsh,        // Complex Multiply and Accumulate Scalar FP16 Values
NN_vfcmulcsh,         // Complex Multiply Scalar FP16 Values
NN_vfmadd132sh,       // Fused Multiply-Add of Scalar FP16 Values
NN_vfmadd213sh,       // Fused Multiply-Add of Scalar FP16 Values
NN_vfmadd231sh,       // Fused Multiply-Add of Scalar FP16 Values
NN_vfmaddcsh,         // Complex Multiply and Accumulate Scalar FP16 Values
NN_vfmsub132sh,       // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfmsub213sh,       // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfmsub231sh,       // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfmulcsh,          // Complex Multiply Scalar FP16 Values
NN_vfnmadd132sh,      // Fused Multiply-Add of Scalar FP16 Values
NN_vfnmadd213sh,      // Fused Multiply-Add of Scalar FP16 Values
NN_vfnmadd231sh,      // Fused Multiply-Add of Scalar FP16 Values
NN_vfnmsub132sh,      // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfnmsub213sh,      // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfnmsub231sh,      // Fused Multiply-Subtract of Scalar FP16 Values
NN_vfpclasssh,        // Test Types of Packed FP16 Values
NN_vgetexpsh,         // Convert Exponents of Packed FP16 Values to FP16 Values
NN_vgetmantsh,        // Extract FP16 Vector of Normalized Mantissas from FP16 Vector
NN_vmaxsh,            // Return Maximum of Scalar FP16 Values
NN_vminsh,            // Return Minimum Scalar FP16 Value
NN_vmovsh,            // Move Scalar FP16 Value
NN_vmulsh,            // Multiply Scalar FP16 Values
NN_vrcpsh,            // Compute Reciprocals of Packed FP16 Values
NN_vreducesh,         // Perform Reduction Transformation on Packed FP16 Values
NN_vrndscalesh,       // Round Packed FP16 Values to Include a Given Number of Fraction Bits
NN_vrsqrtsh,          // Compute Reciprocals of Square Roots of Packed FP16 Values
NN_vscalefsh,         // Scale Packed FP16 Values with FP16 Values
NN_vsqrtsh,           // Compute Square Root of Scalar FP16 Value
NN_vsubsh,            // Subtract Scalar FP16 Value
NN_vucomish,          // Unordered Compare Scalar FP16 Values and Set EFLAGS
// User Interrupt (UINTR)
NN_clui,                // Clear User Interrupt Flag
NN_stui,                // Set User Interrupt Flag
NN_testui,              // Determine User Interrupt Flag
NN_uiret,               // User-Interrupt Return
NN_senduipi,            // Send  User Interprocessor Interrupts
// Prediction history reset (HRESET)
NN_hreset,              // History Reset
// Intel Xeon 6 Granite Rapids microarch PREFETCHI
NN_prefetchit0,         // Prefetch code into all levels of the cache hierarchy
NN_prefetchit1,         // Prefetch code into all but the first-level of the cache hierarchy
// VIA PadLock vendor extension
NN_montmul,             // Montgomery Multiplication
NN_xsha1,               // Hash Function SHA-1
NN_xsha256,             // Hash Function SHA-256
NN_xstore,              // Store Available Random Bytes
NN_xcryptecb,           // AES Electronic Code Book
NN_xcryptcbc,           // AES Cipher Block Chaining
NN_xcryptctr,           // AES Counter Mode
NN_xcryptcfb,           // AES Cipher Feedback Mode
NN_xcryptofb,           // AES Output Feedback Mode
NN_last,
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
I5_null = 0,            // Unknown Operation
//
//      Intel 8080-8085 instructions
//
I5_aci,
I5_adc, Z80_adc = I5_adc,
I5_add, Z80_add = I5_add,
I5_adi,
I5_ana,
I5_ani,
I5_call,
I5_cnz,
I5_cz,
I5_cnc,
I5_cc,
I5_cpo,
I5_cpe,
I5_cp,
I5_cm,
I5_cmc,
I5_cmp,
I5_cpi,
I5_cma,
I5_daa,
I5_dad,
I5_dcr,
I5_dcx,
I5_di, Z80_di = I5_di,
I5_ei, Z80_ei = I5_ei,
I5_halt,
I5_in, Z80_in = I5_in,
I5_inr,
I5_inx,
I5_jmp,
I5_jnz,
I5_jz,
I5_jnc,
I5_jc,
I5_jpo,
I5_jpe,
I5_jp,
I5_jm,
I5_lda,
I5_ldax,
I5_lhld,
I5_lxi,
I5_mov,
I5_mvi,
I5_nop,
I5_ora,
I5_ori,
I5_out, Z80_out = I5_out,
I5_pchl,
I5_pop, Z80_pop = I5_pop,
I5_push, Z80_push = I5_push,
I5_ret,
I5_rnz,
I5_rz,
I5_rnc,
I5_rc,
I5_rpo,
I5_rpe,
I5_rp,
I5_rm,
I5_ral,
I5_rlc,
I5_rar,
I5_rrc,
I5_rst,
I5_sbb,
I5_sbi,
I5_stc,
I5_sphl,
I5_sta,
I5_stax,
I5_shld,
I5_sui,
I5_sub, Z80_sub = I5_sub,
I5_xra,
I5_xri,
I5_xchg,
I5_xthl,
I5_rim,
I5_sim,
//
//      Z80 extensions
//
Z80_and,
Z80_bit,
Z80_call,
Z80_ccf,
Z80_cp,
Z80_cpd,
Z80_cpdr,
Z80_cpi,
Z80_cpir,
Z80_cpl,
Z80_dec,
Z80_djnz,
Z80_ex,
Z80_exx,
Z80_halt,
Z80_im,
Z80_inc,
Z80_ind,
Z80_indr,
Z80_ini,
Z80_inir,
Z80_jp,
Z80_jr,
Z80_ld,
Z80_ldd,
Z80_lddr,
Z80_ldi,
Z80_ldir,
Z80_neg,
Z80_or,
Z80_otdr,
Z80_otir,
Z80_outd,
Z80_outi,
Z80_res,
Z80_ret,
Z80_reti,
Z80_retn,
Z80_rl,
Z80_rla,
Z80_rlc,
Z80_rlca,
Z80_rld,
Z80_rr,
Z80_rra,
Z80_rrc,
Z80_rrca,
Z80_rrd,
Z80_scf,
Z80_sbc,
Z80_set,
Z80_sla,
Z80_sra,
Z80_srl,
Z80_xor,
Z80_inp,                // undocumented
Z80_outp,               // undocumented
Z80_srr,                // undocumented
//
//      HD64180 extensions
//
HD_in0,   Z80_in0   = HD_in0,
HD_mlt,   Z80_mlt   = HD_mlt,
HD_otim,  Z80_otim  = HD_otim,
HD_otimr, Z80_otimr = HD_otimr,
HD_otdm,  Z80_otdm  = HD_otdm,
HD_otdmr, Z80_otdmr = HD_otdmr,
HD_out0,  Z80_out0  = HD_out0,
HD_slp,   Z80_slp   = HD_slp,
HD_tst,   Z80_tst   = HD_tst,
HD_tstio, Z80_tstio = HD_tstio,
//
//      A80 special instructions
//
A80_lbcd,
A80_lded,
A80_lspd,
A80_lixd,
A80_liyd,
A80_sbcd,
A80_sded,
A80_sspd,
A80_sixd,
A80_siyd,
A80_xtix,
A80_xtiy,
A80_spix,
A80_spiy,
A80_pcix,
A80_pciy,
A80_mvra,
A80_mvia,
A80_mvar,
A80_mvai,
A80_addix,
A80_addiy,
A80_addc,
A80_addcix,
A80_addciy,
A80_subc,
A80_subcix,
A80_subciy,
A80_jrc,
A80_jrnc,
A80_jrz,
A80_jrnz,
A80_cmpi,
A80_cmpd,
A80_im0,
A80_im1,
A80_im2,
A80_otd,
A80_oti,
// Intel 8085 undocumented instructions
// (info from http://oak.oakland.edu/pub/cpm/maclib/i8085.lib)
I5_dsub,        // (HL) <- (HL)-(BC), affects all flags
I5_arhl,        // SHIFT HL RIGHT ONE BIT, (H7 IS DUPLICATED, L0 IS SHIFTED INTO CY)
I5_rdel,        // ROTATE DE LEFT ONE BIT THRU CY, (E0 RECEIVES CY, CY RECEIVES D7)
I5_ldhi,        // (DE) <- (HL)+arg
I5_ldsi,        // (DE) <- (SP)+arg
I5_shlx,        // ((DE)) <- (HL)
I5_lhlx,        // (HL) <- ((DE))
I5_rstv,        // RESTART 40H ON V (OVERFLOW)
I5_jx5,         // JUMP IF X5 SET
I5_jnx5,        // JUMP IF NOT X5 SET
// Z380 instructions
Z80_cplw,       // Complement HL register
Z80_swap,       // Swap upper register word with lower register word
Z80_inw,        // Input word
Z80_outw,       // Output word
Z80_ldw,        // Load word
Z80_addw,       // Add word
Z80_subw,       // Subtract word
Z80_adcw,       // Add with carry word
Z80_sbcw,       // Subtract with borrow word
Z80_andw,       // AND logical word
Z80_xorw,       // XOR logical word
Z80_orw,        // OR logical word
Z80_cpw,        // Compare word
Z80_ddir,       // Decoder directive
Z80_calr,       // Call relative
Z80_ldctl,      // Load control register
Z80_mtest,      // Mode test
Z80_exxx,       // Exchange Index Register with Alternate Bank
Z80_exxy,       // Exchange Index Register with Alternate Bank
Z80_exall,      // Exchange all registers with Alternate Bank
Z80_setc,       // Set control bit
Z80_resc,       // Reset control bit
Z80_rlcw,       // Rotate Left Circular Word
Z80_rrcw,       // Rotate Right Circular Word
Z80_rlw,        // Rotate Left Word
Z80_rrw,        // Rotate Right Word
Z80_slaw,       // Shift Left Arithmetic Word
Z80_sraw,       // Shift Right Arithmetic Word
Z80_srlw,       // Shift Right Logical Word
Z80_multw,      // Multiply Word
Z80_multuw,     // Multiply Word Unsigned
Z80_divuw,      // Divide unsigned
Z80_outaw,      // Output word direct to port address
Z80_inaw,       // Input word direct from port address
Z80_outa,       // Output byte direct to port address
Z80_ina,        // Input byte direct from port address
Z80_negw,       // Negate word
Z80_exts,       // Extend byte sign
Z80_extsw,      // Extend word sign
Z80_btest,      // Bank test
Z80_ldiw,       // Load and increment (word)
Z80_ldirw,      // Load and increment, repeat (word)
Z80_lddw,       // Load and decrement (word)
Z80_lddrw,      // Load and decrement, repeat (word)
Z80_iniw,       // Input and increment (word)
Z80_inirw,      // Input and increment, repeat (word)
Z80_indw,       // Input and decrement (word)
Z80_indrw,      // Input and decrement, repeat (word)
Z80_outiw,      // Output and increment (word)
Z80_otirw,      // Output and increment, repeat (word)
Z80_outdw,      // Output and decrement (word)
Z80_otdrw,      // Output and decrement, repeat (word)
// Gameboy instructions
GB_ldh,
GB_stop,
I5_last,
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
I860_null = 0,          // Unknown Operation
//
//      Intel 860 XP instructions
//
I860_adds,
I860_addu,
I860_and,
I860_andh,
I860_andnot,
I860_andnoth,
I860_bc,
I860_bc_t,
I860_bla,
I860_bnc,
I860_bnc_t,
I860_br,
I860_bri,
I860_bte,
I860_btne,
I860_call,
I860_calli,
I860_fadd,
I860_faddp,
I860_faddz,
I860_famov,
I860_fiadd,
I860_fisub,
I860_fix,
I860_fld,
I860_flush,
I860_fmlow_dd,
I860_fmul,
I860_form,
I860_frcp,
I860_frsqr,
I860_fst,
I860_fsub,
I860_ftrunc,
I860_fxfr,
I860_fzchkl,
I860_fzchks,
I860_introvr,
I860_ixfr,
I860_ld_c,
I860_ld,
I860_ldint,
I860_ldio,
I860_lock,
I860_or,
I860_orh,
I860_pfadd,
I860_pfaddp,
I860_pfaddz,
I860_pfamov,
I860_pfeq,
I860_pfgt,
I860_pfiadd,
I860_pfisub,
I860_pfix,
I860_pfld,
I860_pfle,
I860_pfmul,
I860_pfmul3_dd,
I860_pform,
I860_pfsub,
I860_pftrunc,
I860_pfzchkl,
I860_pfzchks,
I860_pst_d,
I860_scyc,
I860_shl,
I860_shr,
I860_shra,
I860_shrd,
I860_st_c,
I860_st,
I860_stio,
I860_subs,
I860_subu,
I860_trap,
I860_unlock,
I860_xor,
I860_xorh,
//
// iNTEL 860 XP Pipelined F-P instructions
//
I860_r2p1,
I860_r2pt,
I860_r2ap1,
I860_r2apt,
I860_i2p1,
I860_i2pt,
I860_i2ap1,
I860_i2apt,
I860_rat1p2,
I860_m12apm,
I860_ra1p2,
I860_m12ttpa,
I860_iat1p2,
I860_m12tpm,
I860_ia1p2,
I860_m12tpa,
I860_r2s1,
I860_r2st,
I860_r2as1,
I860_r2ast,
I860_i2s1,
I860_i2st,
I860_i2as1,
I860_i2ast,
I860_rat1s2,
I860_m12asm,
I860_ra1s2,
I860_m12ttsa,
I860_iat1s2,
I860_m12tsm,
I860_ia1s2,
I860_m12tsa,
I860_mr2p1,
I860_mr2pt,
I860_mr2mp1,
I860_mr2mpt,
I860_mi2p1,
I860_mi2pt,
I860_mi2mp1,
I860_mi2mpt,
I860_mrmt1p2,
I860_mm12mpm,
I860_mrm1p2,
I860_mm12ttpm,
I860_mimt1p2,
I860_mm12tpm,
I860_mim1p2,
I860_mr2s1,
I860_mr2st,
I860_mr2ms1,
I860_mr2mst,
I860_mi2s1,
I860_mi2st,
I860_mi2ms1,
I860_mi2mst,
I860_mrmt1s2,
I860_mm12msm,
I860_mrm1s2,
I860_mm12ttsm,
I860_mimt1s2,
I860_mm12tsm,
I860_mim1s2,
I860_last,
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
I51_null = 0,   // Unknown Operation
I51_acall,      // Absolute Call
I51_add,        // Add Second Operand to Acc
I51_addc,       // Add Second Operand to Acc with carry
I51_ajmp,       // Absolute Jump
I51_anl,        // Logical AND (op1 &= op2)
I51_cjne,       // Compare Operands and JNE
I51_clr,        // Clear Operand (0)
I51_cpl,        // Complement Operand
I51_da,         // Decimal Adjust Accumulator
I51_dec,        // Decrement Operand
I51_div,        // Divide Acc by B
I51_djnz,       // Decrement Operand and JNZ
I51_inc,        // Increment Operand
I51_jb,         // Jump if Bit is set
I51_jbc,        // Jump if Bit is set & clear Bit
I51_jc,         // Jump if Carry is set
I51_jmp,        // Jump indirect relative to Data Pointer
I51_jnb,        // Jump if Bit is clear
I51_jnc,        // Jump if Carry is clear
I51_jnz,        // Jump if Acc is not zero
I51_jz,         // Jump if Acc is zero
I51_lcall,      // Long Subroutine Call
I51_ljmp,       // Long Jump
I51_mov,        // Move (Op1 <- Op2)
I51_movc,       // Move code byte relative to second op to Acc
I51_movx,       // Move from/to external RAM
I51_mul,        // Multiply Acc by B
I51_nop,        // No operation
I51_orl,        // Logical OR (op1 |= op2)
I51_pop,        // Pop  from Stack and put in Direct RAM
I51_push,       // Push from Direct RAM to Stack
I51_ret,        // Return from subroutine
I51_reti,       // Return from Interrupt
I51_rl,         // Rotate Acc left
I51_rlc,        // Rotate Acc left through Carry
I51_rr,         // Rotate Acc right
I51_rrc,        // Rotate Acc right through Carry
I51_setb,       // Set Direct Bit
I51_sjmp,       // Short jump
I51_subb,       // Subtract Second Operand from Acc with Borrow
I51_swap,       // Swap nibbles of Acc
I51_xch,        // Exchange Operands
I51_xchd,       // Exchange Digit in Acc with Indirect RAM
I51_xrl,        // Exclusive OR (op1 ^= op2)
// 80251 instructions
I51_jsle,       // Jump if less than or equal (signed)
I51_jsg,        // Jump if greater than (signed)
I51_jle,        // Jump if less than or equal
I51_jg,         // Jump if greater than
I51_jsl,        // Jump if less than (signed)
I51_jsge,       // Jump if greater than or equal (signed)
I51_je,         // Jump if equal
I51_jne,        // Jump if not equal
I51_trap,       // Trap
I51_ejmp,       // Extended jump
I51_ecall,      // Extended call
I51_eret,       // Extended return
I51_movh,       // Move immediate 16-bit data to the high word of a dword (double-word) register
I51_movz,       // Move 8-bit register to 16-bit register with zero extension
I51_movs,       // Move 8-bit register to 16-bit register with sign extension
I51_srl,        // Shift logical right by 1 bit
I51_sra,        // Shift arithmetic right by 1 bit
I51_sll,        // Shift logical left by 1 bit
I51_sub,        // Subtract
I51_cmp,        // Compare
// 51mx instructions
I51_emov,       // Move (A <- @PRi+disp) or (@PRi+disp <- A)
I51_last,
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
TMS_null = 0,   // Unknown Operation
TMS_abs,        // Absolute value of Acc
TMS_adcb,       // Add ACCB to Acc With Carry
TMS_add,        // Add to Acc
TMS_addb,       // Add ACCB to Acc
TMS_addc,       // Add to Acc With Carry
TMS_adds,       // Add to Acc With Sign-Extension Suppressed
TMS_addt,       // Add to Acc With Shift Specified by TREG1
TMS_adrk,       // Add to Aux Register With Short Immediate
TMS_and,        // AND With Acc
TMS_andb,       // AND ACCD With Acc
TMS_apac,       // Add P Register to Acc
TMS_apl,        // AND Data Memory Value With DBMR
TMS_apl2,       // AND Data Memory Value With Long Constant
TMS_b,          // Branch Unconditionally
TMS_bacc,       // Branch to Location (Acc)
TMS_baccd,      // Branch to Location (Acc) Delayed
TMS_banz,       // Branch on Aux Register Not Zero
TMS_banzd,      // Branch on Aux Register Not Zero Delayed
TMS_bcnd,       // Branch Conditionally
TMS_bcndd,      // Branch Conditionally Delayed
TMS_bd,         // Branch Unconditionally Delayed
TMS_bit,        // Test Bit
TMS_bitt,       // Test Bit Specified by TREG2
TMS_bldd,       // Block Move From Data Memory to Data Memory
TMS_bldp,       // Block Move From Data Memory to Program Memory
TMS_blpd,       // Block Move From Program Memory to Data Memory
TMS_bsar,       // Barrel Shift
TMS_cala,       // Call Subroutine at (Acc)
TMS_calad,      // Call Subroutine at (Acc) Delayed
TMS_call,       // Call Unconditionally
TMS_calld,      // Call Unconditionally Delayed
TMS_cc,         // Call Conditionally
TMS_ccd,        // Call Conditionally Delayed
TMS_clrc,       // Clear Control Bit
TMS_cmpl,       // Complement Acc
TMS_cmpr,       // Compare Aux Register With ARCR
TMS_cpl,        // Compare DBMR With Data Value
TMS_cpl2,       // Compare Long Immediate With Data Value
TMS_crgt,       // Test for Acc Greater Than ACCB
TMS_crlt,       // Test for Acc Smaller Than ACCB
TMS_dmov,       // Data Move in Data Memory
TMS_estop,      // Emulator Stop
TMS_exar,       // Exchange ACCB With Acc
TMS_idle,       // Idle Until Interrupt
TMS_idle2,      // Idle Until Interrupt - Low Power Mode
TMS_in,         // Input Data From Port
TMS_intr,       // Soft Interrupt
TMS_lacb,       // Load Acc With ACCB
TMS_lacc,       // Load Acc With Shift
TMS_lacl,       // Load Low Acc and Clear High Acc
TMS_lact,       // Load Acc With Shift Specified by TREG1
TMS_lamm,       // Load Acc With Memory-Mapped Register
TMS_lar,        // Load Aux Register
TMS_ldp,        // Load Data Memory Pointer
TMS_lmmr,       // Load Memory-Mapped Register
TMS_lph,        // Load Product High Register
TMS_lst,        // Load Status Register
TMS_lt,         // Load TREG0
TMS_lta,        // Load TREG0 and Accumulate Previous Product
TMS_ltd,        // Load TREG0,Accumulate Previous Product and Move Data
TMS_ltp,        // Load TREG0 and Store P -> Acc
TMS_lts,        // Load TREG0 and Subtract Previous Product
TMS_mac,        // Multiply and Accumulate
TMS_macd,       // Multiply and Accumulate With Data Move
TMS_madd,       // Multiply and Accumulate With Data Move and Dynamic Addressing
TMS_mads,       // Multiply and Accumulate With Dynamic Addressing
TMS_mar,        // Modify Aux Register
TMS_mpy,        // Multiply
TMS_mpya,       // Multiply and Accumulate Previous Product
TMS_mpys,       // Multiply and Subtract Previous Product
TMS_mpyu,       // Multiply Unsigned
TMS_neg,        // Negate Acc
TMS_nmi,        // Nonmaskable Interrupt
TMS_nop,        // No Operation
TMS_norm,       // Normalize Contents of Acc
TMS_opl,        // OR With DBMS
TMS_opl2,       // OR With Long Immediate
TMS_or,         // OR With Acc
TMS_orb,        // OR ACCB With Accumulator
TMS_out,        // Out Data to Port
TMS_pac,        // Load Acc <- P
TMS_pop,        // Pop Top of Stack to Low Acc
TMS_popd,       // Pop Top of Stack to Data Memory
TMS_pshd,       // Push Data Memory Value Onto Stack
TMS_push,       // Push Low Acc Onto Stack
TMS_ret,        // Return From Subroutine
TMS_retc,       // Return Conditionally
TMS_retcd,      // Return Conditionally Delayed
TMS_retd,       // Return From Subroutine Delayed
TMS_rete,       // Enable Interrupts and Return From Interrupt
TMS_reti,       // Return From Interrupt
TMS_rol,        // Rotate Acc Left
TMS_rolb,       // Rotate ACCB and Acc Left
TMS_ror,        // Rotate Acc Right
TMS_rorb,       // Rotate ACCB and Acc Right
TMS_rpt,        // Repeat Next Instruction
TMS_rptb,       // Repeat Block
TMS_rptz,       // Repeat Preceded by Clearing Acc and P
TMS_sacb,       // Store Acc in ACCB
TMS_sach,       // Store High Acc With Shift
TMS_sacl,       // Store Low Acc With Shift
TMS_samm,       // Store Acc in Memory-Mapped Register
TMS_sar,        // Store Aux Register
TMS_sath,       // Barrel Shift Acc as Specified by TREG1(4)
TMS_satl,       // Barrel Shift Acc as Specified by TREG1(3-0)
TMS_sbb,        // Subtract ACCB From Acc
TMS_sbbb,       // Subtract ACCB From Acc With Borrow
TMS_sbrk,       // Subtract From Aux Register Short Immediate
TMS_setc,       // Set Control Bit
TMS_sfl,        // Shift Acc Left
TMS_sflb,       // Shift ACCB and Acc Left
TMS_sfr,        // Shift Acc Right
TMS_sfrb,       // Shift ACCB and Acc Right
TMS_smmr,       // Store Memory-Mapped Register
TMS_spac,       // Subtract P From Acc
TMS_sph,        // Store High P Register
TMS_spl,        // Store Low P Register
TMS_splk,       // Store Parallel Long Immediate
TMS_spm,        // Store ACCB and Acc Right
TMS_sqra,       // Square and Accumulate Previous Product
TMS_sqrs,       // Square and Subtract Previous Product
TMS_sst,        // Store Status Register
TMS_sub,        // Subtract From Acc
TMS_subb,       // Subtract From Acc With Borrow
TMS_subc,       // Conditional Subtract
TMS_subs,       // Subtract From Acc With Sign-Extension Suppressed
TMS_subt,       // Subtract From Acc With Shift Specified by TREG1
TMS_tblr,       // Table Read
TMS_tblw,       // Table Write
TMS_trap,       // Software Interrupt
TMS_xc,         // Execute Conditionally
TMS_xor,        // Exclusive-OR With Acc
TMS_xorb,       // Exclusive-OR of ACCB With Acc
TMS_xpl,        // Exclusive-OR Data Memory Value
TMS_xpl2,       // Exclusive-OR Data Memory Value
TMS_zalr,       // Zero Low Acc Load High Acc With Rounding
TMS_zap,        // Zero Acc and P
TMS_zpr,        // Zero P Register
//
//      TMS320C2x instructions
//
TMS2_abs,               // Absolute value of accumulator
TMS2_add,               // Add to accumulator with shift
TMS2_addc,              // Add to accumulator with carry
TMS2_addh,              // Add to high accumulator
TMS2_addk,              // Add to accumulator short immediate
TMS2_adds,              // Add to low accumulator with sign extension suppressed
TMS2_addt,              // Add to accumulator with shift specified by T register
TMS2_adlk,              // Add to accumulator long immediate with shift
TMS2_adrk,              // Add to auxiliary register short immediate
TMS2_and,               // And with accumulator
TMS2_andk,              // And immediate with accumulator with shift
TMS2_apac,              // App P register to accumulator
TMS2_b,                 // Branch unconditionally
TMS2_bacc,              // Branch to address specified by accumulator
TMS2_banz,              // Bnrach on auxiliary register not zero
TMS2_bbnz,              // Branch if tc bit != 0
TMS2_bbz,               // Branch if tc bit = 0
TMS2_bc,                // Branch on carry
TMS2_bgez,              // Branch if accumulator >= 0
TMS2_bgz,               // Branch if accumulator > 0
TMS2_bioz,              // Branch on i/o status = 0
TMS2_bit,               // Test bit
TMS2_bitt,              // Test bit specifed by T register
TMS2_blez,              // Branch if accumulator <= 0
TMS2_blkd,              // Block move from data memory to data memory
TMS2_blkp,              // Block move from program memory to data memory
TMS2_blz,               // Branch if accumulator < 0
TMS2_bnc,               // Branch on no carry
TMS2_bnv,               // Branch if no overflow
TMS2_bnz,               // Branch if accumulator != 0
TMS2_bv,                // Branch on overflow
TMS2_bz,                // Branch if accumulator = 0
TMS2_cala,              // Call subroutine indirect
TMS2_call,              // Call subroutine
TMS2_cmpl,              // Complement accumulator
TMS2_cmpr,              // Compare auxiliary register with auxiliary register ar0
TMS2_cnfd,              // Configure block as data memory
TMS2_cnfp,              // Configure block as program memory
TMS2_conf,              // Configure block as data/program memory
TMS2_dint,              // Disable interrupt
TMS2_dmov,              // Data move in data memory
TMS2_eint,              // Enable interrupt
TMS2_fort,              // Format serial port registers
TMS2_idle,              // Idle until interrupt
TMS2_in,                // Input data from port
TMS2_lac,               // Load accumulator with shift
TMS2_lack,              // Load accumulator short immediate
TMS2_lact,              // Load accumulator with shift specified by T register
TMS2_lalk,              // Load accumulator long immediate with shift
TMS2_lar,               // Load auxiliary register
TMS2_lark,              // Load auxiliary register short immediate
TMS2_larp,              // Load auxiliary register pointer
TMS2_ldp,               // Load data memory page pointer
TMS2_ldpk,              // Load data memory page pointer immediate
TMS2_lph,               // Load high P register
TMS2_lrlk,              // Load auxiliary register long immediate
TMS2_lst,               // Load status register ST0
TMS2_lst1,              // Load status register ST1
TMS2_lt,                // Load T register
TMS2_lta,               // Load T register and accumulate previous product
TMS2_ltd,               // Load T register, accumulate previous product and move data
TMS2_ltp,               // Load T register and store P register in accumulator
TMS2_lts,               // Load T register and subtract previous product
TMS2_mac,               // Multiply and accumulate
TMS2_macd,              // Multiply and accumulate with data move
TMS2_mar,               // Modify auxiliary register
TMS2_mpy,               // Multiply (with T register, store product in P register)
TMS2_mpya,              // Multiply and accumulate previous product
TMS2_mpyk,              // Multiply immediate
TMS2_mpys,              // Multiply and subtract previous product
TMS2_mpyu,              // Multiply unsigned
TMS2_neg,               // Negate accumulator
TMS2_nop,               // No operation
TMS2_norm,              // Normalize contents of accumulator
TMS2_or,                // Or with accumulator
TMS2_ork,               // Or immediate with accumulator with shift
TMS2_out,               // Output data to port
TMS2_pac,               // Load accumulator with P register
TMS2_pop,               // Pop top of stack to low accumulator
TMS2_popd,              // Pop top of stack to data memory
TMS2_pshd,              // Push data memory value onto stack
TMS2_push,              // Push low accumulator onto stack
TMS2_rc,                // Reset carry bit
TMS2_ret,               // Return from subroutine
TMS2_rfsm,              // Reset serial port frame synchronization mode
TMS2_rhm,               // Reset hold mode
TMS2_rol,               // Rotate accumulator left
TMS2_ror,               // Rotate acuumulator right
TMS2_rovm,              // Reset overflow mode
TMS2_rpt,               // Repeat instruction as specified by data memory value
TMS2_rptk,              // Repeat instruction as specified by immediate value
TMS2_rsxm,              // Reset sign extension mode
TMS2_rtc,               // Reset test/control flag
TMS2_rtxm,              // Reset serial port transmit mode
TMS2_rxf,               // Reset external flag
TMS2_sach,              // Store high accumulator with shift
TMS2_sacl,              // Store low accumulator with shift
TMS2_sar,               // Store auxiliary register
TMS2_sblk,              // Subtract from accumulator long immediate with shift
TMS2_sbrk,              // Subtract from auxiliary register short immediate
TMS2_sc,                // Set carry bit
TMS2_sfl,               // Shift accumulator left
TMS2_sfr,               // Shift accumulator right
TMS2_sfsm,              // Set serial port frame synchronization mode
TMS2_shm,               // Set hold mode
TMS2_sovm,              // Set overflow mode
TMS2_spac,              // Subtract P register from accumulator
TMS2_sph,               // Store high P register
TMS2_spl,               // Store low P register
TMS2_spm,               // Set P register output shift mode
TMS2_sqra,              // Square and accumulate
TMS2_sqrs,              // Square and subtract previous product
TMS2_sst,               // Store status register ST0
TMS2_sst1,              // Store status register ST1
TMS2_ssxm,              // Set sign extension mode
TMS2_stc,               // Set test/control flag
TMS2_stxm,              // Set serial port transmit mode
TMS2_sub,               // Subtract from accumulator with shift
TMS2_subb,              // Subtract from accumulator with borrow
TMS2_subc,              // Conditional subtract
TMS2_subh,              // Subtract from high accumulator
TMS2_subk,              // Subtract from accumulator shoft immediate
TMS2_subs,              // Subtract from low accumulator with sign extension suppressed
TMS2_subt,              // Subtract from accumulator with shift specified by T register
TMS2_sxf,               // Set external flag
TMS2_tblr,              // Table read
TMS2_tblw,              // Table write
TMS2_trap,              // Software interrupt
TMS2_xor,               // Exclusive or with accumulator
TMS2_xork,              // Exclusive or immediate with accumulator with shift
TMS2_zac,               // Zero accumulator
TMS2_zalh,              // Zero low accumulator and load high accumulator
TMS2_zalr,              // Zero low accumulator and load high accumulator with rounding
TMS2_zals,              // Zero low accumulator and load high accumulator with sign extension suppressed
TMS_last,
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
  M65_null = 0,           // Unknown Operation
  // NMOS instructions
  M65_adc,                // A <- (A) + M + C
  M65_anc,                // A <- A /\ M, C <- ~A7
  M65_and,                // A <- (A) /\ M
  M65_ane,                // M <-[(A)\/$EE] /\ (X)/\‍(M)
  M65_arr,                // A <- [(A /\ M) >> 1]
  M65_asl,                // C <- A7, A <- (A) << 1
  M65_asr,                // A <- [(A /\ M) >> 1]
  M65_bcc,                // if C=0, PC = PC + offset
  M65_bcs,                // if C=1, PC = PC + offset
  M65_beq,                // if Z=1, PC = PC + offset
  M65_bit,                // Z <- ~(A /\ M) N<-M7 V<-M6
  M65_bmi,                // if N=1, PC = PC + offset
  M65_bne,                // if Z=0, PC = PC + offset
  M65_bpl,                // if N=0, PC = PC + offset
  M65_brk,                // Stack <- PC, PC <- ($fffe)
  M65_bvc,                // if V=0, PC = PC + offset
  M65_bvs,                // if V=1, PC = PC + offset
  M65_clc,                // C <- 0
  M65_cld,                // D <- 0
  M65_cli,                // I <- 0
  M65_clv,                // V <- 0
  M65_cmp,                // (A - M) -> NZC
  M65_cpx,                // (X - M) -> NZC
  M65_cpy,                // (Y - M) -> NZC
  M65_dcp,                // M <- (M)-1, (A-M) -> NZC
  M65_dec,                // M <- (M) - 1
  M65_dex,                // X <- (X) - 1
  M65_dey,                // Y <- (Y) - 1
  M65_eor,                // A <- (A) \-/ M
  M65_inc,                // M <- (M) + 1
  M65_inx,                // X <- (X) +1
  M65_iny,                // Y <- (Y) + 1
  M65_isb,                // M <- (M) - 1,A <- (A)-M-~C
  M65_jmp,                // PC <- Address
  M65_jmpi,               // (PC <- Address)
  M65_jsr,                // Stack <- PC, PC <- Address
  M65_lae,                // X,S,A <- (S /\ M)
  M65_lax,                // A <- M, X <- M
  M65_lda,                // A <- M
  M65_ldx,                // X <- M
  M65_ldy,                // Y <- M
  M65_lsr,                // C <- A0, A <- (A) >> 1
  M65_lxa,                // X04 <- (X04) /\ M04, A04 <- (A04) /\ M04
  M65_nop,                // [no operation]
  M65_ora,                // A <- (A) V M
  M65_pha,                // Stack <- (A)
  M65_php,                // Stack <- (P)
  M65_pla,                // A <- (Stack)
  M65_plp,                // A <- (Stack)
  M65_rla,                // M <- (M << 1) /\ (A)
  M65_rol,                // C <- A7 & A <- A << 1 + C
  M65_ror,                // C<-A0 & A<- (A7=C + A>>1)
  M65_rra,                // M <- (M >> 1) + (A) + C
  M65_rti,                // P <- (Stack), PC <-(Stack)
  M65_rts,                // PC <- (Stack)
  M65_sax,                // M <- (A) /\ (X)
  M65_sbc,                // A <- (A) - M - ~C
  M65_sbx,                // X <- (X)/\‍(A) - M
  M65_sec,                // C <- 1
  M65_sed,                // D <- 1
  M65_sei,                // I <- 1
  M65_sha,                // M <- (A) /\ (X) /\ (PCH+1)
  M65_shs,                // X <- (A) /\ (X), S <- (X), M <- (X) /\ (PCH+1)
  M65_shx,                // M <- (X) /\ (PCH+1)
  M65_shy,                // M <- (Y) /\ (PCH+1)
  M65_slo,                // M <- (M >> 1) + A + C
  M65_sre,                // M <- (M >> 1) \-/ A
  M65_sta,                // M <- (A)
  M65_stx,                // M <- (X)
  M65_sty,                // M <- (Y)
  M65_tax,                // X <- (A)
  M65_tay,                // Y <- (A)
  M65_tsx,                // X <- (S)
  M65_txa,                // A <- (X)
  M65_txs,                // S <- (X)
  M65_tya,                // A <- (Y)
  // CMOS instructions
  M65_bbr0,               // Branch if bit 0 reset
  M65_bbr1,               // Branch if bit 1 reset
  M65_bbr2,               // Branch if bit 2 reset
  M65_bbr3,               // Branch if bit 3 reset
  M65_bbr4,               // Branch if bit 4 reset
  M65_bbr5,               // Branch if bit 5 reset
  M65_bbr6,               // Branch if bit 6 reset
  M65_bbr7,               // Branch if bit 7 reset
  M65_bbs0,               // Branch if bit 0 set
  M65_bbs1,               // Branch if bit 1 set
  M65_bbs2,               // Branch if bit 2 set
  M65_bbs3,               // Branch if bit 3 set
  M65_bbs4,               // Branch if bit 4 set
  M65_bbs5,               // Branch if bit 5 set
  M65_bbs6,               // Branch if bit 6 set
  M65_bbs7,               // Branch if bit 7 set
  M65_rmb0,               // Reset memory bit 0
  M65_rmb1,               // Reset memory bit 1
  M65_rmb2,               // Reset memory bit 2
  M65_rmb3,               // Reset memory bit 3
  M65_rmb4,               // Reset memory bit 4
  M65_rmb5,               // Reset memory bit 5
  M65_rmb6,               // Reset memory bit 6
  M65_rmb7,               // Reset memory bit 7
  M65_smb0,               // Set memory bit 0
  M65_smb1,               // Set memory bit 1
  M65_smb2,               // Set memory bit 2
  M65_smb3,               // Set memory bit 3
  M65_smb4,               // Set memory bit 4
  M65_smb5,               // Set memory bit 5
  M65_smb6,               // Set memory bit 6
  M65_smb7,               // Set memory bit 7
  M65_stz,                // Store zero
  M65_tsb,                // Test and set bits
  M65_trb,                // Test and reset bits
  M65_phy,                // Push Y register
  M65_ply,                // Pull Y register
  M65_phx,                // Push X register
  M65_plx,                // Pull X register
  M65_bra,                // Branch always
  M65_wai,                // Wait for interrupt
  M65_stp,                // Stop processor
  M65_last,
};
// The instruction types (``itype''s)
// m65* CPUs implements.
enum m65_itype_t
{
  // http://www.westerndesigncenter.com/wdc/datasheets/Programmanual.pdf
  M65816_null=0, // Unknown Operation
  M65816_adc,    // Add with carry
  M65816_and,    // AND A with memory
  M65816_asl,    // Shift memory or A left
  M65816_bcc,    // Branch if carry clear
  M65816_bcs,    // Branch if carry set
  M65816_beq,    // Branch if equal
  M65816_bit,    // Test memory bits against A
  M65816_bmi,    // Branch if minus
  M65816_bne,    // Branch if not equal
  M65816_bpl,    // Branch if plus
  M65816_bra,    // Branch always
  M65816_brk,    // Software break
  M65816_brl,    // Branch always long
  M65816_bvc,    // Branch if overflow clear
  M65816_bvs,    // Branch if overflow set
  M65816_clc,    // Clear carry flag
  M65816_cld,    // Clear decimal mode flag
  M65816_cli,    // Clear interrupt disable flag
  M65816_clv,    // Clear overflow flag
  M65816_cmp,    // Compare A with memory
  M65816_cop,    // Co-processor enable
  M65816_cpx,    // Compare X with memory
  M65816_cpy,    // Compare Y with memory
  M65816_dec,    // Decrement
  M65816_dex,    // Decrement X
  M65816_dey,    // Decrement Y
  M65816_eor,    // XOR A with M
  M65816_inc,    // Increment
  M65816_inx,    // Increment X
  M65816_iny,    // Increment Y
  M65816_jml,    // Jump long (inter-bank)
  M65816_jmp,    // Jump
  M65816_jsl,    // Jump to subroutine long (inter-bank)
  M65816_jsr,    // Jump to subroutine
  M65816_lda,    // Load A from memory
  M65816_ldx,    // Load X from memory
  M65816_ldy,    // Load Y from memory
  M65816_lsr,    // Logical shift memory or A right
  M65816_mvn,    // Block move next
  M65816_mvp,    // Block move prev
  M65816_nop,    // Nop
  M65816_ora,    // Or A with memory
  M65816_pea,    // Push effective absolute address
  M65816_pei,    // Push effective indirect address
  M65816_per,    // Push effective PC-relative indirect address
  M65816_pha,    // Push A
  M65816_phb,    // Push B (data bank register)
  M65816_phd,    // Push D (direct page register)
  M65816_phk,    // Push K (program bank register)
  M65816_php,    // Push processor status
  M65816_phx,    // Push X
  M65816_phy,    // Push Y
  M65816_pla,    // Pull A
  M65816_plb,    // Pull B
  M65816_pld,    // Pull D
  M65816_plp,    // Pull processor status
  M65816_plx,    // Pull X
  M65816_ply,    // Pull Y
  M65816_rep,    // Reset status bits
  M65816_rol,    // Rotate memory or A left
  M65816_ror,    // Rotate memory or A right
  M65816_rti,    // Return from interrupt
  M65816_rtl,    // Return from subroutine long
  M65816_rts,    // Return from subroutine
  M65816_sbc,    // Subtract with borrow from A
  M65816_sec,    // Set carry flag
  M65816_sed,    // Set decimal mode flag
  M65816_sei,    // Set interrupt disable flag
  M65816_sep,    // Set status bits
  M65816_sta,    // Store A to memory
  M65816_stp,    // Stop processor
  M65816_stx,    // Store X to memory
  M65816_sty,    // Store Y to memory
  M65816_stz,    // Store zero to memory
  M65816_tax,    // Transfer A to X
  M65816_tay,    // Transfer A to Y
  M65816_tcd,    // Transfer 16-bit A to D (direct page register)
  M65816_tcs,    // Transfer A to S
  M65816_tdc,    // Transfer 16-bit D to A
  M65816_trb,    // Test and reset memory bits against A
  M65816_tsb,    // Test and set memory bits against A
  M65816_tsc,    // Transfer S to A
  M65816_tsx,    // Transfer S to X
  M65816_txa,    // Transfer X to A
  M65816_txs,    // Transfer X to S
  M65816_txy,    // Transfer X to Y
  M65816_tya,    // Transfer Y to A
  M65816_tyx,    // Transfer Y to X
  M65816_wai,    // Wait for interrupt
  M65816_wdm,    // Reserved
  M65816_xba,    // Exchange bytes in A
  M65816_xce,    // Exchange carry and emulation bits
  M65816_last
};
/*
 *      Interactive disassembler (IDA)
 *      Copyright (c) 1990-2026 Hex-Rays
 *      PDP11 module.
 *      Copyright (c) 1995-2006 by Iouri Kharon.
 *                        E-mail: yjh@styx.cabel.net
 *
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
pdp_null = 0,           // Unknown Operation
pdp_halt,       // Stop CPU
pdp_wait,       // Wait interrupt
pdp_rti,        // Interrupt return
pdp_bpt,        // Trap to Debbuger
pdp_iot,        // Trap to 20 (i/o)
pdp_reset,      // Reset CPU and device
pdp_rtt,        // Interrupt return and ignore dbg-flag
pdp_mfpt,       // Load Processor Type          (* hi model)
pdp_jmp,        // Absolute jmp
pdp_rts,        // Return into subroutine
pdp_spl,        // Set Prior.
pdp_nop,        // Not operation
pdp_clc,        // Clear C bit in PSW
pdp_clv,        // Clear V bit in PSW
pdp_clz,        // Clear Z bit in PSW
pdp_cln,        // Clear N bit in PSW
pdp_ccc,        // Clear All Condition bits in PSW
pdp_sec,        // Set C bit in PSW
pdp_sev,        // Set V bit in PSW
pdp_sez,        // Set Z bit in PSW
pdp_sen,        // Set N bit in PSW
pdp_scc,        // Set All Condition bits bit in PSW
pdp_swab,       // Exchange byte in word
pdp_br,         // Relative jmp
pdp_bne,        // Jump if Z=0
pdp_beq,        // Jump if Z=1
pdp_bge,        // Jump if N^V=0
pdp_blt,        // Jump if N^V=1
pdp_bgt,        // Jump if Z|(N^V)=0
pdp_ble,        // Jump if Z|(N^V)=1
pdp_jsr,        // Call procedure
pdp_clr,        // Clear operand
pdp_com,        // Inverse operand
pdp_inc,        // Increment operand
pdp_dec,        // Decrement operand
pdp_neg,        // op = -op
pdp_adc,        // Add with Carry
pdp_sbc,        // Substract with Carry
pdp_tst,        // Test operand
pdp_ror,        // Cyclic shift rignt
pdp_rol,        // Cyclic shift left
pdp_asr,        // Arifmetic shift rignt
pdp_asl,        // Arifmetic shift left
pdp_mark,       // Return and empty stack
pdp_mfpi,       // Load from previous instruction space (*hi model)
pdp_mtpi,       // Store to previous instruction space  (*hi model)
pdp_sxt,        // N=>op
pdp_mov,        // Move operand
pdp_cmp,        // Compare operands
pdp_bit,        // Check Bit's
pdp_bic,        // Clear Bit's
pdp_bis,        // Set Bit's
pdp_add,        // Add operands
pdp_sub,        // Substract operands
pdp_mul,        // Multiple Reg          (*eis)
pdp_div,        // Divide Reg            (*eis)
pdp_ash,        // Multistep shift       (*eis)
pdp_ashc,       // Multistep shift 2 reg (*eis)
pdp_xor,        // Exclusive or          (*eis)
pdp_fadd,       // Floating Add         (*fis)
pdp_fsub,       // Floating Subtract    (*fis)
pdp_fmul,       // Floating Multiple    (*fis)
pdp_fdiv,       // Floating Divide      (*fis)
pdp_sob,        //
pdp_bpl,        // Jump if N=0
pdp_bmi,        // Jump if N=1
pdp_bhi,        // Jump if (!C)&(!Z)=0
pdp_blos,       // Jump if C|Z=1
pdp_bvc,        // Jump if V=0
pdp_bvs,        // Jump if V=1
pdp_bcc,        // Jump if C=0
pdp_bcs,        // Jump if C=1
pdp_emt,        // Trap to System
pdp_trap,       // Trap to user/compiler
pdp_mtps,       // Store PSW            (*lsi11 only)
pdp_mfpd,       // Load from previous data space (*hi model)
pdp_mtpd,       // Store to previous data space  (*hi model)
pdp_mfps,       // Load  PSW            (*lsi11 only)
    // FPU instruction
pdp_cfcc,       // Copy cond.codes into FPS to PSW
pdp_setf,       // Set Float
pdp_seti,       // Set Integer
pdp_setd,       // Set Double
pdp_setl,       // Set Long Integer
pdp_ldfps,      // Load FPS
pdp_stfps,      // Store FPS
pdp_stst,       // Load interrupt status
pdp_clrd,       // Clear
pdp_tstd,       // Test
pdp_absd,       // op = mod(op)
pdp_negd,       // op = -op
pdp_muld,       // Multiple
pdp_modd,       // Get int. part
pdp_addd,       // Add
pdp_ldd,        // Load in Acc
pdp_subd,       // Substract
pdp_cmpd,       // Compare
pdp_std,        // Store into Acc
pdp_divd,       // Divide
pdp_stexp,      // Store exponent
pdp_stcdi,      // Store and convert double/float to integer/long
pdp_stcdf,      // Store and convert double/float to float/double
pdp_ldexp,      // Load exponent
pdp_ldcif,      // Load and convert integer/long to double/float
pdp_ldcfd,      // Load and convert float/double to double/float
pdp_call,       // Jsr PC,
pdp_return,     // RTS PC
pdp_compcc,     // Complex Condition Codes
pdp_last
    };
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
  mc_null = 0,   // Unknown Operation
  mc_abcd,       // summa with BCD correction
  mc_add,        // summa with Dn
  mc_adda,       // summa with An
  mc_addi,       // summa with immediate
  mc_addq,       // -"-
  mc_addx,       // summa 2 reg and const
  mc_and,        // logical and
  mc_andi,       // logical and with immediate
  mc_asl,        // shift by count
  mc_asr,        // -"-
  mc_b,          // branch if cond code
  mc_bchg,       // bit chang
  mc_bclr,       // bit clear
  mc_bftst,      // bit field test
  mc_bfchg,      // bit field change
  mc_bfclr,      // bit field set in 0
  mc_bfset,      // bit field set in 1
  mc_bfextu,     // bit field extract (unsigned)
  mc_bfexts,     // bit field extract (signed)
  mc_bfffo,      // bit field offset
  mc_bfins,      // bit field include
  mc_bgnd,       // CPU32- enter backgound mode
  mc_bkpt,       // disable TRAP at any cycles
  mc_bra,        // branch
  mc_bset,       // bit set
  mc_bsr,        // relative call
  mc_btst,       // bit test
  mc_callm,      // call module [descrtiptor] (020)
  mc_cas,        // compare and swap
  mc_cas2,       // -"-
  mc_chk,        // compare and trap
  mc_chk2,       // -"-
  mc_cinv,       // invalidate cache
  mc_clr,        // clear data
  mc_cmp,        // compare data
  mc_cmp2,       // -"-
  mc_cmpa,       // compare address
  mc_cmpi,       // compare immediate
  mc_cmpm,       // compare memory
  mc_cpush,      // invalidate cache
  mc_db,         // (djnz) if cond code
  mc_divs,       // sign divide
  mc_divsl,      // -"-
  mc_divu,       // unsign didide
  mc_divul,      // -"-
  mc_eor,        // logical xor
  mc_eori,       // logical xor with immediate
  mc_exg,        // exchange registers
  mc_ext,        // analog cwd
  mc_extb,       // analog cwq
  mc_fabs,       // FP abs
  mc_facos,      // FP acos
  mc_fadd,       // FP add
  mc_fasin,      // FP asin
  mc_fatan,      // FP atan
  mc_fatanh,     // FP atanh
  mc_fb,         // fBcc
  mc_fcmp,       // FP cmp
  mc_fcos,       // FP cos
  mc_fcosh,      // FP cosh
  mc_fdabs,      // FP abs double rounded
  mc_fdadd,      // FP add
  mc_fdb,        // fDBcc
  mc_fddiv,      // FP div double rounded
  mc_fdiv,       // FP div
  mc_fdmove,     // FP mov double rounded
  mc_fdmul,      // FP mul double rounded
  mc_fdneg,      // FP neg double rounded
  mc_fdsqrt,     // FP sqrt double rounded
  mc_fdsub,      // FP sub double rounded
  mc_fetox,      // FP e**x
  mc_fetoxm1,    // FP e**x-1
  mc_fgetexp,    // FP extract exponent
  mc_fgetman,    // FP extract mantissa
  mc_fint,       // FP get integer part
  mc_fintrz,     // FP get integer part by round
  mc_flog2,      // FP log[2]
  mc_flog10,     // FP log[10]
  mc_flogn,      // FP log[e]
  mc_flognp1,    // FP log[e] x+1
  mc_fmod,       // FP mod
  mc_fmove,      // move float
  mc_fmovecr,    // move floating const
  mc_fmovem,     // move float register list
  mc_fmul,       // FM mul
  mc_fneg,       // FP neg
  mc_fnop,       // float nop
  mc_frem,       // FP rem
  mc_frestore,   // restore status
  mc_fs,         // fScc
  mc_fsabs,      // FP abs single rounded
  mc_fsadd,      // FP add single rounded
  mc_fsave,      // Fsave status
  mc_fscale,     // FP *2**x
  mc_fsdiv,      // FP div single rounded
  mc_fsgldiv,    // FP single div
  mc_fsglmul,    // FP single mul
  mc_fsin,       // FP sin
  mc_fsincos,    // FP sin & cos
  mc_fsinh,      // FP sinh
  mc_fsmove,     // FP mov single rounded
  mc_fsmul,      // FP mul single rounded
  mc_fsneg,      // FP neg single rounded
  mc_fsqrt,      // FP sqrt
  mc_fssqrt,     // FP sqrt single rounded
  mc_fssub,      // FP sub single rounded
  mc_fsub,       // FP sub
  mc_ftan,       // FP tan
  mc_ftanh,      // FP tanh
  mc_ftentox,    // FP 10**x
  mc_ftrap,      // fTRAPcc
  mc_ftst,       // FP tst
  mc_ftwotox,    // FP 2**x
  mc_halt,       // (coldfire) Halt the processor
  mc_illegal,    // trap to vector
  mc_jmp,        // absolute Jmp
  mc_jsr,        // absolute jsr
  mc_lea,        // load effective address
  mc_link,       // change sp context
  mc_lpstop,     // cpu32 - stop
  mc_lsl,        // logical shift
  mc_lsr,        // -"-
  mc_mac,        // multiple and accumulate
  mc_macl,       // multiple and accumulate with register load
  mc_move,       // move memory
  mc_move16,     // move 16 byte
  mc_movea,      // move move with address reg
  mc_movec,      // move from/to control register
  mc_movem,      // move register list
  mc_movep,      // move with data register
  mc_moveq,      // move with immediate
  mc_moves,      // mtpd/mfpd
  mc_msac,       // multiple and subtract
  mc_msacl,      // multiple and subtract with register load
  mc_muls,       // sign multiplication
  mc_mulu,       // unsign multiplication
  mc_nbcd,       // negative with BCD correct
  mc_neg,        // negative
  mc_negx,       // negative with immediate
  mc_nop,        // null operation
  mc_not,        // logical not
  mc_or,         // logical or
  mc_ori,        // logical or with immediate
  mc_pack,       // UNP(bcd)+adj -> PACK(bcd)
  mc_pea,        // lea into stack
  mc_pb,         // 68851 pbcc
  mc_pdb,        // 68851 pdbcc
  mc_pflush,     // invalidate cache
  mc_pflushr,    // 68851 load root entry
  mc_ploadr,     // 68851
  mc_ploadw,     // 68851
  mc_pmove,      // move MMU register
  mc_prestore,   // 68851
  mc_psave,      // 68851
  mc_ps,         // 68851 pscc
  mc_ptestr,     // test a logical address
  mc_ptestw,     // -"-
  mc_ptrap,      // 68851 ptrapcc
  mc_pulse,      // (coldfire) generate unique PST value
  mc_pvalid,     // 68851 move AL bit
  mc_rol,        // cycl. shift
  mc_ror,        // -"-
  mc_roxl,       // two op cycl shift
  mc_roxr,       // -"-
  mc_reset,      // reset
  mc_rtd,        // mark
  mc_rte,        // return with SR
  mc_rtm,        // reload save module state
  mc_rtr,        // return with CCR
  mc_rts,        // return
  mc_sbcd,       // substract with BCD correction
  mc_s,          // 1 if cond code else 0
  mc_stop,       // halt
  mc_sub,        // substract
  mc_suba,       // substract address
  mc_subi,       // substract immediate
  mc_subq,       // -"-
  mc_subx,       // substract memory
  mc_swap,       // hi and low word in register
  mc_tas,        // test byte sign
  mc_tbl,        // CPU32-tblu/tblun/tbls/tblsn
  mc_trap,       // analog int(86) (or trap if cond code)
  mc_trapv,      // if V then trap
  mc_tst,        // test destination
  mc_unlk,       // destroy address ?
  mc_unpk,       // PACK(bcd)+adj -> UNPACK(bcd)
  mc_wddata,     // (coldfire) load WDDATA port (pins)
  mc_wdebug,     // (coldfire) load debug register
  mc_atrap,      // MacOS atrap
  // new ColdFire instructions
  mc_bitrev,     // bit reverse
  mc_byterev,    // byte reverse
  mc_ff1,        // find first one
  mc_intouch,    // instruction fetch touch
  mc_mov3q,      // move 3-bit data quick
  mc_mvs,        // move with sign extend
  mc_mvz,        // move with zero-fill
  mc_sats,       // signed saturate
  mc_movclr,     // move from accumulator and clear
  mc_maaac,      // Multiply and Add to 1st Accumulator, Add to 2nd Accumulator
  mc_masac,      // Multiply and Add to 1st Accumulator, Subtract from 2nd Accumulator
  mc_msaac,      // Multiply and Subtract to 1st Accumulator, Add to 2nd Accumulator
  mc_mssac,      // Multiply and Subtract to 1st Accumulator, Subtract to 2nd Accumulator
  mc_remsl,      // Signed Divide Remainder
  mc_remul,      // Unsigned Divide Remainder
  mc_last
};
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
mc8_null = 0,           // Unknown Operation
mc8_aba,        // Add b to a                                  (11)
mc8_ab,         // Add b to index register
mc8_adc,        // Add with carry
mc8_add,        // Add without carry
mc8_addd,       // Add 16-bit to D                             (11)
mc8_ais,        // Add immediate value to stack pointer        (8)
mc8_aix,        // Add immediate value to index register (H:X) (8)
mc8_and,        // Logical AND
mc8_andcc,      // Logical AND immdiate with CCR (9)
mc8_asr,        // Ariphmetic shift right
mc8_bcc,        // Branch if carry bit clear
mc8_bclr,       // Clear bit in memory
mc8_bcs,        // Branch if carry bit set
mc8_beq,        // Branch if equal
mc8_bge,        // Branch if >= (signed)
mc8_bgt,        // Branch if > (signed)
mc8_bhcc,       // Branch if half carry bit clear (8)
mc8_bhcs,       // Branch if half carry bit set   (8)
mc8_bhi,        // Branch if > (unsigned)
mc8_bhs,        // Branch if >= (unsigned)        (11)
mc8_bih,        // Branch if IRQ pin high         (8)
mc8_bil,        // Branch if IRQ pin low          (8)
mc8_bit,        // Bit test                       (8)
mc8_ble,        // Branch if <= (signed)          (8)
mc8_blo,        // Branch if <  (unsigned)        (11)
mc8_bls,        // Branch if <= (unsigned)        (8)
mc8_blt,        // Branch if < (signed)           (8)
mc8_bmc,        // Branch if interrupt mask clear (8)
mc8_bmi,        // Branch if minus
mc8_bms,        // Branch if interrupt mask set   (8)
mc8_bne,        // Branch if not equal
mc8_bpl,        // Branch if not plus
mc8_bra,        // Branch always
mc8_brclr,      // Branch if bit (n) in memory clear
mc8_brn,        // Branch never
mc8_brset,      // Branch if bit (n) in memory set
mc8_bset,       // Set bit in memory
mc8_bsr,        // Branch to subroutine
mc8_bvc,        // Branch if overflow cleared     (11)
mc8_bvs,        // Branch if overflow set         (11)
mc8_cba,        // Compare A to B                 (11)
mc8_cbeq,       // Compare and branch if equal    (8)
mc8_clc,        // Clear carry bit
mc8_cli,        // Clear interrupt mask
mc8_clr,        // Clear
mc8_clv,        // Clear overflow flag            (11)
mc8_cmp,        // Compare accumulator with memory
mc8_com,        // Complement
mc8_cp,         // Compare index register 16 bit  (11)
mc8_cpd,        // Compare D 16 bit               (11)
mc8_cphx,       // Compare index register with memory          (8)
mc8_cpx,        // Compare X (index register low) with memory  (8)
mc8_cwai,       // Clear CC bits & wait for interrupt          (9)
mc8_daa,        // Decimal adjust accumulator
mc8_dbnz,       // Decrement and branch if not equal   (8)
mc8_de,         // Decrement index register            (11)
mc8_dec,        // Decrement
mc8_des,        // Decrement stack pointer             (11)
mc8_div,        // Divide                              (8)
mc8_eor,        // Excusive OR memory with accumulator
mc8_exg,        // Exchange register                   (9)
mc8_fdiv,       // Fractional divide 16 by 16          (11)
mc8_idiv,       // Integer divide 16 by 16             (11)
mc8_in,         // Increment index register            (11)
mc8_inc,        // Increment
mc8_ins,        // Increment stack pointer             (11)
mc8_jmp,        // Jump
mc8_jsr,        // Jump to subroutine
mc8_ld,         // Load index register                     (11)
mc8_lda,        // Load accumulator from memory
mc8_ldd,        // Load double accumulator                 (11)
mc8_ldhx,       // Load index register from memory         (8)
mc8_lds,        // Load stack pointer                      (11)
mc8_ldx,        // Load X (index register low) from memory (8)
mc8_lea,        // Load register from memory               (9)
mc8_lsl,        // Logical (or Ariphmetic) shift left
mc8_lsld,       // Logical (or Ariphmetic) shift left double (11)
mc8_lsr,        // Logical shift right
mc8_lsrd,       // Logical shift right double                (11)
mc8_mov,        // Move                          (8)
mc8_mul,        // Unsigned multiply
mc8_neg,        // Negate
mc8_nop,        // No Operation
mc8_nsa,        // Nibble swap accumulator       (8)
mc8_ora,        // Inclusive OR memory with accumulator
mc8_orcc,       // Inclusive OR immediate with CCR            (9)
mc8_psh,        // Push index register into stack (low first) (11)
mc8_psha,       // Push accumulator A into stack
mc8_pshb,       // Push accumulator B into stack              (11)
mc8_pshh,       // Push H (index register high) into stack    (8)
mc8_pshx,       // Push X (index register low) into stack     (8)
mc8_pul,        // Pull index register from stack (hi first)  (11)
mc8_pula,       // Pull accumulator A from stack
mc8_pulb,       // Pull accumulator B from stack              (11)
mc8_pulh,       // Pull H (index register high) from stack    (8)
mc8_pulx,       // Pull X (index register low) from stack     (8)
mc8_rol,        // Rotate left trough carry
mc8_ror,        // Rotate right trough carry
mc8_rsp,        // Reset stack pointer               (8)
mc8_rti,        // Reset from interrupt
mc8_rts,        // Reset from subroutine
mc8_sba,        // Subtract B from A                       (11)
mc8_sbc,        // Subtract with carry
mc8_sec,        // Set carry bit
mc8_sei,        // Set interrupt mask bit
mc8_sev,        // Set Overflow Flag                       (11)
mc8_sex,        // Sign extended                           (9)
mc8_slp,        // Sleep    (HD63701 extention)            (11)
mc8_st,         // Store index register in memory          (11)
mc8_sta,        // Store accumulator in memory
mc8_std,        // Store accumulators in memory            (11)
mc8_sthx,       // Store H:X (index reg)                   (8)
mc8_stop,       // Enable IRQ pin. Stop oscillator
mc8_sts,        // Store stack pointer                     (11)
mc8_stx,        // Store X (index register low) in memory  (8)
mc8_sub,        // Subtract
mc8_subd,       // Subtract 16-bit                         (11)
mc8_swi,        // Software interrupt
mc8_sync,       // Syncronisation with interrupt           (9)
mc8_tab,        // Transfer A to B                                (11)
mc8_tap,        // Transfer A to CCR
mc8_tax,        // Transfer accumulator to X (index register low) (8)
mc8_tba,        // Transfer B to A                                (11)
mc8_test,       // Address Bus Counts (in test mode)              (11)
mc8_tfr,        // Transfer register to register                  (9)
mc8_tpa,        // Transfer CCR to A
mc8_ts,         // Transfer SP to index reg                       (11)
mc8_tst,        // Test for negative or zero
mc8_tsx,        // Transfer SP to index reg                       (8)
mc8_txa,        // Transfer X (index reg low) to accumulator      (8)
mc8_txs,        // Transfer index reg X to SP
mc8_tys,        // Transfer index reg Y to SP                     (11)
mc8_wai,        // Wait for interrupt                   (11)
mc8_wait,       // Enable interrupt. Stop processor     (8)
mc8_xgd,        // Exchange D with index register       (11)
mc8_1,          // Special testing command              (11)
mc8_2,          // Special testing command              (11)
mc8_os9,        // OS9 system call                      (9)
// these instructions must be continuous (HD63701 extention)
mc8_aim,
mc8_oim,
mc8_eim,
mc8_tim,
// new S08 instructions
mc8_bgnd,       // Background                                     (8)
mc8_call,       // Call Subroutine                                (8)
mc8_rtc,        // Return fom Call                                (8)
// Pseudoinstructions
mc8_skip1,      // Skip one byte
mc8_skip2,      // Skip two bytes
mc8_last
    };
/*
 *      Interactive disassembler (IDA)
 *      Copyright (c) 1990-2026 Hex-Rays
 *      JVM module.
 *      Copyright (c) 1995-2006 by Iouri Kharon.
 *                        E-mail: yjh@styx.cabel.net
 *
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
  j_nop = 0,        //   0 Do nothing
  j_aconst_null,    //   1 Push null object reference
  j_iconst_m1,      //   2 Push integer constant -1
  j_iconst_0,       //   3 Push the integer 0
  j_iconst_1,       //   4 Push the integer 1
  j_iconst_2,       //   5 Push the integer 2
  j_iconst_3,       //   6 Push the integer 3
  j_iconst_4,       //   7 Push the integer 4
  j_iconst_5,       //   8 Push the integer 5
  j_lconst_0,       //   9 Push the long integer 0
  j_lconst_1,       //  10 Push the long integer 1
  j_fconst_0,       //  11 Push the single-precision foating point 0.0
  j_fconst_1,       //  12 Push the single-precision foating point 1.0
  j_fconst_2,       //  13 Push the single-precision foating point 2.0
  j_dconst_0,       //  14 Push the double-precision foating point 2.0
  j_dconst_1,       //  15 Push the double-precision foating point 2.0
  j_bipush,         //  16 Push one byte signed integer
  j_sipush,         //  17 Push two-byte signed integer
  j_ldc,            //  18 Push item from constant pool (i1)
  j_ldcw,           //  19 Push item from constant pool (i2)
  j_ldc2w,          //  20 Push long or double from constant pool
  j_iload,          //  21 Push integer value of the local variable
  j_lload,          //  22 Push long value of the local variable
  j_fload,          //  23 Push single float value of the local variable
  j_dload,          //  24 Push double float value of the local variable
  j_aload,          //  25 Push object reference from the local variable
  j_iload_0,        //  26 Push integer value of the local variable #0
  j_iload_1,        //  27 Push integer value of the local variable #1
  j_iload_2,        //  28 Push integer value of the local variable #2
  j_iload_3,        //  29 Push integer value of the local variable #3
  j_lload_0,        //  30 Push long value of the local variable #0
  j_lload_1,        //  31 Push long value of the local variable #1
  j_lload_2,        //  32 Push long value of the local variable #2
  j_lload_3,        //  33 Push long value of the local variable #3
  j_fload_0,        //  34 Push single float value of the local variable #0
  j_fload_1,        //  35 Push single float value of the local variable #1
  j_fload_2,        //  36 Push single float value of the local variable #2
  j_fload_3,        //  37 Push single float value of the local variable #3
  j_dload_0,        //  38 Push double float value of the local variable #0
  j_dload_1,        //  39 Push double float value of the local variable #1
  j_dload_2,        //  40 Push double float value of the local variable #2
  j_dload_3,        //  41 Push double float value of the local variable #3
  j_aload_0,        //  42 Push object reference from the local variable #0
  j_aload_1,        //  43 Push object reference from the local variable #1
  j_aload_2,        //  44 Push object reference from the local variable #2
  j_aload_3,        //  45 Push object reference from the local variable #3
  j_iaload,         //  46 Push integer from array
  j_laload,         //  47 Push long from array
  j_faload,         //  48 Push single float from array
  j_daload,         //  49 Push double float from array
  j_aaload,         //  50 Push object refernce from array
  j_baload,         //  51 Push signed byte from array
  j_caload,         //  52 Push character from array
  j_saload,         //  53 Push short from array
  j_istore,         //  54 Pop integer value into local variable
  j_lstore,         //  55 Pop long value into local variable
  j_fstore,         //  56 Pop single float value into local variable
  j_dstore,         //  57 Pop double float value into local variable
  j_astore,         //  58 Pop object refernce into local variable
  j_istore_0,       //  59 Pop integer value into local variable #0
  j_istore_1,       //  60 Pop integer value into local variable #1
  j_istore_2,       //  61 Pop integer value into local variable #2
  j_istore_3,       //  62 Pop integer value into local variable #3
  j_lstore_0,       //  63 Pop long value into local variable #0
  j_lstore_1,       //  64 Pop long value into local variable #1
  j_lstore_2,       //  65 Pop long value into local variable #2
  j_lstore_3,       //  66 Pop long value into local variable #3
  j_fstore_0,       //  67 Pop single float value into local variable #0
  j_fstore_1,       //  68 Pop single float value into local variable #1
  j_fstore_2,       //  69 Pop single float value into local variable #2
  j_fstore_3,       //  70 Pop single float value into local variable #3
  j_dstore_0,       //  71 Pop double float value into local variable
  j_dstore_1,       //  72 Pop double float value into local variable #0
  j_dstore_2,       //  73 Pop double float value into local variable #1
  j_dstore_3,       //  74 Pop double float value into local variable #2
  j_astore_0,       //  75 Pop object refernce into local variable #0
  j_astore_1,       //  76 Pop object refernce into local variable #1
  j_astore_2,       //  77 Pop object refernce into local variable #2
  j_astore_3,       //  78 Pop object refernce into local variable #3
  j_iastore,        //  79 Pop integer from array
  j_lastore,        //  80 Pop long from array
  j_fastore,        //  81 Pop single float from array
  j_dastore,        //  82 Pop double float from array
  j_aastore,        //  83 Pop object refernce from array
  j_bastore,        //  84 Pop signed byte from array
  j_castore,        //  85 Pop character from array
  j_sastore,        //  86 Pop short from array
  j_pop,            //  87 Pop top stack word
  j_pop2,           //  88 Pop top two stack word
  j_dup,            //  89 Duplicate top stack word
  j_dup_x1,         //  90 Duplicate top stack word and put two down
  j_dup_x2,         //  91 Duplicate top stack word and put three down
  j_dup2,           //  92 Duplicate top two stack word
  j_dup2_x1,        //  93 Duplicate top two stack words and put two down
  j_dup2_x2,        //  94 Duplicate top two stack words and put three down
  j_swap,           //  95 Swap two top stack words
  j_iadd,           //  96 Integer add
  j_ladd,           //  97 Long add
  j_fadd,           //  98 Single float add
  j_dadd,           //  99 Double float add
  j_isub,           // 100 Integer subtract
  j_lsub,           // 101 Long subtract
  j_fsub,           // 102 Single float subtract
  j_dsub,           // 103 Double Float subtract
  j_imul,           // 104 Integer multiply
  j_lmul,           // 105 Long multiply
  j_fmul,           // 106 Single float multiply
  j_dmul,           // 107 Double Float multiply
  j_idiv,           // 108 Integer divide
  j_ldiv,           // 109 Long divide
  j_fdiv,           // 110 Single float divide
  j_ddiv,           // 111 Double Float divide
  j_irem,           // 112 Integer reminder
  j_lrem,           // 113 Long reminder
  j_frem,           // 114 Single float reminder
  j_drem,           // 115 Double Float reminder
  j_ineg,           // 116 Integer negate
  j_lneg,           // 117 Long negate
  j_fneg,           // 118 Single float negate
  j_dneg,           // 119 Double Float negate
  j_ishl,           // 120 Integer shift left
  j_lshl,           // 121 Long shift left
  j_ishr,           // 122 Integer logical shift right
  j_lshr,           // 123 Long logical shift right
  j_iushr,          // 124 Integer arithmetic shift right
  j_lushr,          // 125 Long arithmeticshift right
  j_iand,           // 126 Integer boolean AND
  j_land,           // 127 Long boolean AND
  j_ior,            // 128 Integer boolean OR
  j_lor,            // 129 Long boolean OR
  j_ixor,           // 130 Integer boolean XOR
  j_lxor,           // 131 Long boolean XOR
  j_iinc,           // 132 Add 8-bit signed const to local variable
  j_i2l,            // 133 Integer to Long conversion
  j_i2f,            // 134 Integer to single float conversion
  j_i2d,            // 135 Integer to double float conversion
  j_l2i,            // 136 Long to Integer conversion
  j_l2f,            // 137 Long to single float conversion
  j_l2d,            // 138 Long to double float conversion
  j_f2i,            // 139 Single float to Integer conversion
  j_f2l,            // 140 Single float to Long conversion
  j_f2d,            // 141 Single float to double float conversion
  j_d2i,            // 142 Double float to Integer conversion
  j_d2l,            // 143 Double float to Long conversion
  j_d2f,            // 144 Double float to double float conversion
  j_i2b,            // 145 Integer to signed byte conversion
  j_i2c,            // 146 Integer to unsigned short conversion
  j_i2s,            // 147 Integer to signed short conversion
  j_lcmp,           // 148 Long compare
  j_fcmpl,          // 149 Single float compare (-1 on NaN)
  j_fcmpg,          // 150 Single float compare (1 on NaN)
  j_dcmpl,          // 151 Double float compare (-1 on NaN)
  j_dcmpg,          // 152 Double float compare (1 on NaN)
  j_ifeq,           // 153 Branch if equal to 0
  j_ifne,           // 154 Branch if not equal to 0
  j_iflt,           // 155 Branch if less then 0
  j_ifge,           // 156 Branch if greater than or equal to 0
  j_ifgt,           // 157 Branch if greater than 0
  j_ifle,           // 158 Branch if less than or equal to 0
  j_if_icmpeq,      // 159 Branch if integers equal
  j_if_icmpne,      // 160 Branch if integers not equal
  j_if_icmplt,      // 161 Branch if integers less than
  j_if_icmpge,      // 162 Branch if integers grater than or equal to
  j_if_icmpgt,      // 163 Branch if integers grater than
  j_if_icmple,      // 164 Branch if integers less than or equal to
  j_if_acmpeq,      // 165 Branch if object references are equal
  j_if_acmpne,      // 166 Branch if object references not equal
  j_goto,           // 167 Branch always
  j_jsr,            // 168 Jump subroutine
  j_ret,            // 169 Return from subroutine
  j_tableswitch,    // 170 Access jump table by index and jump
  j_lookupswitch,   // 171 Access jump table by key match and jump
  j_ireturn,        // 172 Return integer from function
  j_lreturn,        // 173 Return long from function
  j_freturn,        // 174 Return single floatr from function
  j_dreturn,        // 175 Return double float from function
  j_areturn,        // 176 Return object reference from function
  j_return,         // 177 Return (void) from procedure
  j_getstatic,      // 178 Set static field from class
  j_putstatic,      // 179 Set static field in class
  j_getfield,       // 180 Fetch field from object
  j_putfield,       // 181 Set field in object
  j_invokevirtual,  // 182 invoke instance method
  j_invokespecial,  // 183 invoke instance method (superclass/init/...)
  j_invokestatic,   // 184 invoke a class (static) method
  j_invokeinterface,// 185 invoke interface method
  j_invokedynamic,  // 186 invoke instance method (select by paraneter)
  j_new,            // 187 Create new object
  j_newarray,       // 188 Allocate new array
  j_anewarray,      // 189 Allocate new array of refernces to object
  j_arraylength,    // 190 Get length of array
  j_athrow,         // 191 Throw exception or error
  j_checkcast,      // 192 Make sure object is of given type
  j_instanceof,     // 193 Determine if an object is of given type
  j_monitorenter,   // 194 Enter monitored region of code
  j_monitorexit,    // 195 Exit monitored region of code
  j_wide,           // 196 wide (prefix of command)
  j_multianewarray, // 197  Allocate new multi-dimensional array
  j_ifnull,         // 198 Branch if NULL-ptr
  j_ifnonnull,      // 199 Branch if not NULL-ptr
  j_goto_w,         // 200 Branch always (wide index)
  j_jsr_w,          // 201 Jump subroutine (wide index)
  j_breakpoint,     // 202 Stop and pass control to breakpoint handler
  //
  j_lastnorm,
  j_a_invokesuper = j_lastnorm,
  j_a_invokevirtualobject,
  j_a_invokeignored,
  // bottom of table ! (emu)
  j_a_software,
  j_a_hardware,
  //
  j_last
};
enum name_quick
{
  j_ldc_quick = j_lastnorm,    // 203     (18)
  j_ldcw_quick,                // 204     (19)
  j_ldc2w_quick,               // 205     (20)
  j_getfield_quick,            // 206     (180)
  j_putfield_quick,            // 207     (181)
  j_getfield2_quick,           // 208
  j_putfield2_quick,           // 209
  j_getstatic_quick,           // 210     (178)
  j_putstatic_quick,           // 211     (179)
  j_getstatic2_quick,          // 212
  j_putstatic2_quick,          // 213
  j_invokevirtual_quick,       // 214     (182)
  j_invokenonvirtual_quick,    // 215     (183)
  j_invokesuper_quick,         // 216
  j_invokestatic_quick,        // 217     (184)
  j_invokeinterface_quick,     // 218     (185)
  j_invokevirtualobject_quick, // 219
  j_invokeignored_quick,       // 220
  j_new_quick,                 // 221     (187)
  j_anewarray_quick,           // 222     (189)
  j_multianewarray_quick,      // 223     (197)
  j_checkcast_quick,           // 224     (192)
  j_instanceof_quick,          // 225     (193)
  j_invokevirtual_quick_w,     // 226
  j_getfield_quick_w,          // 227
  j_putfield_quick_w,          // 228
  j_quick_last
};
/*
 *      Interactive disassembler (IDA).
 *      Copyright (c) 1990-2026 Hex-Rays
 *      ALL RIGHTS RESERVED.
 *
 */
enum
{
ARM_null = 0,           // Unknown Operation
ARM_ret,                // Return from Subroutine
ARM_nop,                // No Operation
ARM_b,                  // Branch
ARM_bl,                 // Branch with Link
ARM_asr,                // Arithmetic Shift Right
ARM_lsl,                // Logical Shift Left
ARM_lsr,                // Logical Shift Right
ARM_ror,                // Rotate Right
ARM_neg,                // Negate
ARM_and,                // 0 Rd = Op1 & Op2
ARM_eor,                // 1 Rd = Op1 ^ Op2
ARM_sub,                // 2 Rd = Op1 - Op2
ARM_rsb,                // 3 Rd = Op2 - Op1
ARM_add,                // 4 Rd = Op1 + Op2
ARM_adc,                // 5 Rd = Op1 + Op2 + C
ARM_sbc,                // 6 Rd = Op1 - Op2 + C - 1
ARM_rsc,                // 7 Rd = Op2 - Op1 + C - 1
ARM_tst,                // 8 Set cond. codes on Op1 & Op2
ARM_teq,                // 9 Set cond. codes on Op1 ^ Op2
ARM_cmp,                // A Set cond. codes on Op1 - Op2
ARM_cmn,                // B Set cond. codes on Op1 + Op2
ARM_orr,                // C Rd = Op1 | Op2
ARM_mov,                // D Rd = Op2
ARM_bic,                // E Rd = Op1 & ~Op2
ARM_mvn,                // F Rd = ~Op2
ARM_mrs,                // Transfer PSR to Register
ARM_msr,                // Transfer Register to PSR
ARM_mul,                // Multiply
ARM_mla,                // Multiply-Accumulate
ARM_ldr,                // Load from Memory
ARM_ldrpc,              // Indirect Jump
ARM_str,                // Store to Memory
ARM_ldm,                // Load Block from Memory
ARM_stm,                // Store Block to Memory
ARM_swp,                // Single Data Swap
ARM_svc,                // Supervisor call
// Version 4
ARM_smull,              // Signed Multiply long
ARM_smlal,              // Signed Multiply-Accumulate long
ARM_umull,              // Unsigned Multiply long
ARM_umlal,              // Unsigned Multiply-Accumulate long
ARM_bx,                 // Branch to/from Thumb mode
ARM_pop,                // Pop registers
ARM_push,               // Push registers
ARM_adr,                // Load address
// Version 5
ARM_bkpt,               // Breakpoint
ARM_blx1,               // Branch with Link and Exchange (immediate address)
ARM_blx2,               // Branch with Link and Exchange (register indirect)
ARM_clz,                // Count Leading Zeros
// Version 5E
ARM_ldrd,               // Load pair of registers
ARM_pld,                // Prepare to load data
ARM_qadd,               // Saturated addition
ARM_qdadd,              // Saturated addition with doubling
ARM_qdsub,              // Saturated subtraction with doubling
ARM_qsub,               // Saturated subtraction
ARM_smlabb,             // Signed multiply-accumulate (bottom*bottom)
ARM_smlatb,             // Signed multiply-accumulate (top*bottom)
ARM_smlabt,             // Signed multiply-accumulate (bottom*top)
ARM_smlatt,             // Signed multiply-accumulate (top*top)
ARM_smlalbb,            // Long signed multiply-accumulate (bottom*bottom)
ARM_smlaltb,            // Long signed multiply-accumulate (top*bottom)
ARM_smlalbt,            // Long signed multiply-accumulate (bottom*top)
ARM_smlaltt,            // Long signed multiply-accumulate (top*top)
ARM_smlawb,             // Wide signed multiply-accumulate (bottom)
ARM_smulwb,             // Wide signed multiply (bottom)
ARM_smlawt,             // Wide signed multiply-accumulate (top)
ARM_smulwt,             // Wide signed multiply (top)
ARM_smulbb,             // Signed multiply (bottom*bottom)
ARM_smultb,             // Signed multiply (top*bottom)
ARM_smulbt,             // Signed multiply (bottom*top)
ARM_smultt,             // Signed multiply (top*top)
ARM_strd,               // Store pair of registers
// Intel xScale coprocessor instructions
xScale_mia,             // Multiply-Internal Accumulate
xScale_miaph,           // Multiply-Internal Accumulate Packed HalfWords
xScale_miabb,           // Multiply-Internal Accumulate Bottom-Bottom Halves
xScale_miabt,           // Multiply-Internal Accumulate Bottom-Top Halves
xScale_miatb,           // Multiply-Internal Accumulate Top-Bottom Halves
xScale_miatt,           // Multiply-Internal Accumulate Top-Top Halves
xScale_mar,             // Move To Internal Accumulator
xScale_mra,             // Move From Internal Accumulator
// Macro instructions
ARM_movl,               // Move immediate to register
ARM_adrl,               // Load address
ARM_swbkpt,             // WinCE Debugger break
// Coprocessor instructions
ARM_cdp,                // Coprocessor Data Processing
ARM_cdp2,               // Coprocessor Data Processing
ARM_ldc,                // Load Coprocessor Register
ARM_ldc2,               // Load Coprocessor Register
ARM_stc,                // Store Coprocessor Register
ARM_stc2,               // Store Coprocessor Register
ARM_mrc,                // Move from Coprocessor to ARM Register
ARM_mrc2,               // Move from Coprocessor to ARM Register
ARM_mcr,                // Move from ARM to Coprocessor Register
ARM_mcr2,               // Move from ARM to Coprocessor Register
ARM_mcrr,               // Copy pair of registers to coprocessor (5E)
ARM_mrrc,               // Copy pair of registers from coprocessor (5E)
// VFP instructions
ARM_fabsd,              // Floating point Absolute Value, Double precision
ARM_fabss,              // Floating point Absolute Value, Single precision
ARM_faddd,              // Floating point Addition, Double precision
ARM_fadds,              // Floating point Addition, Single precision
ARM_fcmpd,              // Floating point Compare, Double precision
ARM_fcmps,              // Floating point Compare, Single precision
ARM_fcmped,             // Floating point Compare (NaN Exceptions), Double precision
ARM_fcmpes,             // Floating point Compare (NaN Exceptions), Single precision
ARM_fcmpezd,            // Floating point Compare (NaN Exceptions) with Zero, Double precision
ARM_fcmpezs,            // Floating point Compare (NaN Exceptions) with Zero, Single precision
ARM_fcmpzd,             // Floating point Compare with Zero, Double precision
ARM_fcmpzs,             // Floating point Compare with Zero, Single precision
ARM_fcpyd,              // Floating point Copy, Double precision
ARM_fcpys,              // Floating point Copy, Single precision
ARM_fcvtsd,             // Floating point Convert to Single precision from Double precision
ARM_fcvtds,             // Floating point Convert to Double precision from Single precision
ARM_fdivd,              // Floating point Divide, Double precision
ARM_fdivs,              // Floating point Divide, Single precision
ARM_fldd,               // Floating point Load, Double precision
ARM_flds,               // Floating point Load, Single precision
ARM_fldmd,              // Floating point Load Multiple, Double precision
ARM_fldms,              // Floating point Load Multiple, Single precision
ARM_fldmx,              // Floating point Load Multiple, Unknown precision
ARM_fmacd,              // Floating point Multiply and Accumulate, Double precision
ARM_fmacs,              // Floating point Multiply and Accumulate, Single precision
ARM_fmscd,              // Floating point Multiply and Subtract, Double precision
ARM_fmscs,              // Floating point Multiply and Subtract, Single precision
ARM_fmstat,             // Floating point Move Status
ARM_fmuld,              // Floating point Multiply, Double precision
ARM_fmuls,              // Floating point Multiply, Single precision
ARM_fnegd,              // Floating point Negate, Double precision
ARM_fnegs,              // Floating point Negate, Single precision
ARM_fnmacd,             // Floating point Negated Multiply and Accumulate, Double precision
ARM_fnmacs,             // Floating point Negated Multiply and Accumulate, Single precision
ARM_fnmscd,             // Floating point Negated Multiply and Subtract, Double precision
ARM_fnmscs,             // Floating point Negated Multiply and Subtract, Single precision
ARM_fnmuld,             // Floating point Negated Multiply, Double precision
ARM_fnmuls,             // Floating point Negated Multiply, Single precision
ARM_fsitod,             // Floating point Convert Signed Integer to Double precision
ARM_fsitos,             // Floating point Convert Signed Integer to Single precision
ARM_fsqrtd,             // Floating point Square Root, Double precision
ARM_fsqrts,             // Floating point Square Root, Single precision
ARM_fstd,               // Floating point Store, Double precision
ARM_fsts,               // Floating point Store, Single precision
ARM_fstmd,              // Floating point Store Multiple, Double precision
ARM_fstms,              // Floating point Store Multiple, Single precision
ARM_fstmx,              // Floating point Store Multiple, Unknown precision
ARM_fsubd,              // Floating point Subtract, Double precision
ARM_fsubs,              // Floating point Subtract, Single precision
ARM_ftosid,             // Floating point Convert to Signed Integer from Double precision
ARM_ftosis,             // Floating point Convert to Signed Integer from Single precision
ARM_ftosizd,            // Floating point Convert to Signed Integer from Double precision, RZ mode
ARM_ftosizs,            // Floating point Convert to Signed Integer from Single precision, RZ mode
ARM_ftouid,             // Floating point Convert to Unsigned Integer from Double precision
ARM_ftouis,             // Floating point Convert to Unsigned Integer from Single precision
ARM_ftouizd,            // Floating point Convert to Unsigned Integer from Double precision, RZ mode
ARM_ftouizs,            // Floating point Convert to Unsigned Integer from Single precision, RZ mode
ARM_fuitod,             // Floating point Convert Unsigned Integer to Double precision
ARM_fuitos,             // Floating point Convert Unsigned Integer to Single precision
ARM_fmdhr,              // Floating point Move to Double precision High from Register
ARM_fmrdh,              // Floating point Move to Register from Double precision High
ARM_fmdlr,              // Floating point Move to Double precision Low from Register
ARM_fmrdl,              // Floating point Move to Register from Double precision Low
ARM_fmxr,               // Floating point Move to System Register from Register
ARM_fmrx,               // Floating point Move to Register from System Register
ARM_fmsr,               // Floating point Move to Single precision from Register
ARM_fmrs,               // Floating point Move to Register from Single precision
// VFP ARMv5TE extensions
ARM_fmdrr,              // Floating point Move to Double precision from two Registers
ARM_fmrrd,              // Floating point Move to two Registers from Double precision
ARM_fmsrr,              // Floating point Move to two Single precision from two Registers
ARM_fmrrs,              // Floating point Move to two Registers from two Single precision
// ARM v5J instructions
ARM_bxj,                // Branch to Jazelle
// ARM v6 instructions
ARM_mcrr2,              // Move to Coprocessor from two ARM Registers
ARM_mrrc2,              // Move to two ARM Registers from Coprocessor
ARM_cps,                // Change Processor State
ARM_cpsid,              // Disable Interrupts
ARM_cpsie,              // Enable Interrupts
ARM_ldrex,              // Load Register Exclusive
ARM_pkhbt,              // Pack halfword bottom + top
ARM_pkhtb,              // Pack halfword top + bottom
ARM_qadd16,             // Signed saturating arithmetic hafword-wise addition
ARM_qadd8,              // Signed saturating arithmetic byte-wise addition
ARM_qasx,               // Saturating Add and Subtract with Exchange
ARM_qaddsubx=ARM_qasx,  // Signed saturating arithmetic exchange, add, substract (old name)
ARM_qsub16,             // Signed saturating arithmetic hafword-wise substraction
ARM_qsub8,              // Signed saturating arithmetic byte-wise substraction
ARM_qsax,               // Saturating Subtract and Add with Exchange
ARM_qsubaddx=ARM_qsax,  // Signed saturating arithmetic exchange, substract, add (old name)
ARM_rev,                // Byte Reverse Word
ARM_rev16,              // Byte Reverse Packed Halfword
ARM_revsh,              // Byte Reverse Signed Halfword
ARM_rfe,                // Return from exception
ARM_sadd16,             // Signed arithmetic modulo hafword-wise addition
ARM_sadd8,              // Signed arithmetic modulo byte-wise addition
ARM_sasx,               // Signed Add and Subtract with Exchange
ARM_saddsubx=ARM_sasx,  // Signed arithmetic modulo exchange, add, substract (old name)
ARM_sel,                // Select bytes
ARM_setend,             // Set Byte Endianness
ARM_shadd16,            // Signed arithmetic hafword-wise addition, halving results
ARM_shadd8,             // Signed arithmetic byte-wise addition, halving results
ARM_shasx,              // Signed Halving Add and Subtract with Exchange
ARM_shaddsubx=ARM_shasx,// Signed arithmetic exchange, add, substract, halving results (old name)
ARM_shsub16,            // Signed arithmetic hafword-wise substraction, halving results
ARM_shsub8,             // Signed arithmetic byte-wise substraction, halving results
ARM_shsax,              // Signed Halving Subtract and Add with Exchange
ARM_shsubaddx=ARM_shsax,// Signed arithmetic exchange, substract, add, halving results (old name)
ARM_smlad,              // Dual signed multiply, add and accumulate
ARM_smladx,             // Dual signed multiply, add and accumulate crossed
ARM_smuad,              // Dual signed multiply and add
ARM_smuadx,             // Dual signed multiply and add crossed
ARM_smlald,             // Dual signed multiply, add and accumulate long
ARM_smlaldx,            // Dual signed multiply, add and accumulate long crossed
ARM_smlsd,              // Dual signed multiply, substract and accumulate
ARM_smlsdx,             // Dual signed multiply, substract and accumulate crossed
ARM_smusd,              // Dual signed multiply and substract
ARM_smusdx,             // Dual signed multiply and substract crossed
ARM_smlsld,             // Dual signed multiply, substract and accumulate long
ARM_smlsldx,            // Dual signed multiply, substract and accumulate long crossed
ARM_smmla,              // Signed most significant word multiply and accumulate truncated
ARM_smmlar,             // Signed most significant word multiply and accumulate rounded
ARM_smmul,              // Signed most significant word multiply truncated
ARM_smmulr,             // Signed most significant word multiply rounded
ARM_smmls,              // Signed most significant word multiply and substract truncated
ARM_smmlsr,             // Signed most significant word multiply and substract rounded
ARM_srs,                // Store Return State
ARM_ssat,               // Signed Saturate
ARM_ssat16,             // Signed saturate two halfwords
ARM_ssub16,             // Signed arithmetic hafword-wise substraction
ARM_ssub8,              // Signed arithmetic byte-wise substraction
ARM_ssax,               // Signed Subtract and Add with Exchange
ARM_ssubaddx=ARM_ssax,  // Signed arithmetic exchange, substract, add (old name)
ARM_strex,              // Store Register Exclusive
ARM_sxtab,              // Signed extend byte to word, add
ARM_sxtb,               // Signed extend byte to word
ARM_sxtab16,            // Signed extend two bytes to halfwords, add
ARM_sxtb16,             // Signed extend two bytes to halfwords
ARM_sxtah,              // Signed extend halfword to word, add
ARM_sxth,               // Signed extend halfword to word
ARM_uadd16,             // Unsigned arithmetic modulo hafword-wise addition
ARM_uadd8,              // Unsigned arithmetic modulo byte-wise addition
ARM_uasx,               // Unsigned Add and Subtract with Exchange
ARM_uaddsubx=ARM_uasx,  // Unsigned arithmetic modulo exchange, add, substract (old name)
ARM_uhadd16,            // Unsigned arithmetic hafword-wise addition, halving results
ARM_uhadd8,             // Unsigned arithmetic byte-wise addition, halving results
ARM_uhasx,              // Unsigned Halving Add and Subtract with Exchange
ARM_uhaddsubx=ARM_uhasx,// Unsigned arithmetic exchange, add, substract, halving results (old name)
ARM_uhsub16,            // Unsigned arithmetic hafword-wise substraction, halving results
ARM_uhsub8,             // Unsigned arithmetic byte-wise substraction, halving results
ARM_uhsax,              // Unsigned Halving Subtract and Add with Exchange
ARM_uhsubaddx=ARM_uhsax,// Unsigned arithmetic exchange, substract, add, halving results (old name)
ARM_umaal,              // Multiply unsigned double accumulate long
ARM_uqadd16,            // Unsigned saturating arithmetic hafword-wise addition
ARM_uqadd8,             // Unsigned saturating arithmetic byte-wise addition
ARM_uqasx,              // Unsigned Saturating Add and Subtract with Exchange
ARM_uqaddsubx=ARM_uqasx,// Unsigned saturating arithmetic exchange, add, substract (old name)
ARM_uqsub16,            // Unsigned saturating arithmetic hafword-wise substraction
ARM_uqsub8,             // Unsigned saturating arithmetic byte-wise substraction
ARM_uqsax,              // Unsigned Saturating Subtract and Add with Exchange
ARM_uqsubaddx=ARM_uqsax,// Unsigned saturating arithmetic exchange, substract, add (old name)
ARM_usada8,             // Unsigned sum of absolute differences and accumulate
ARM_usad8,              // Unsigned sum of absolute differences
ARM_usat,               // Unsigned saturate word
ARM_usat16,             // Unsigned saturate two halfwords
ARM_usub16,             // Unsigned arithmetic hafword-wise substraction
ARM_usub8,              // Unsigned arithmetic byte-wise substraction
ARM_usax,               // Unsigned Subtract and Add with Exchange
ARM_usubaddx=ARM_usax,  // Unsigned arithmetic exchange, substract, add (old name)
ARM_uxtab,              // Unsigned extend byte to word, add
ARM_uxtb,               // Unsigned extend byte to word
ARM_uxtab16,            // Unsigned extend two bytes to halfwords, add
ARM_uxtb16,             // Unsigned extend two bytes to halfwords
ARM_uxtah,              // Unsigned extend halfword to word, add
ARM_uxth,               // Unsigned extend halfword to word
// ARM v6zk instructions
ARM_clrex,              // Clear Exclusive
ARM_ldrexb,             // Load Byte Exclusive
ARM_ldrexd,             // Load DoubleWord Exclusive
ARM_ldrexh,             // Load Halfword Exclusive
ARM_strexb,             // Store Byte Exclusive
ARM_strexd,             // Store DoubleWord Exclusive
ARM_strexh,             // Store Halfword Exclusive
ARM_yield,              // Yield (hint)
ARM_sev,                // Send Event (hint)
ARM_wfe,                // Wait For Event (hint)
ARM_wfi,                // Wait For Interrupt (hint)
ARM_smc,                // Secure Monitor Call
// ARM Thumb32 instructions
ARM_orn,                // Rd = Op1 | ~Op2
ARM_movt,               // Move Top
ARM_sbfx,               // Signed Bit Field Extract
ARM_ubfx,               // Unsigned Bit Field Extract
ARM_bfi,                // Bit Field Insert
ARM_bfc,                // Bit Field Clear
ARM_tbb,                // Table Branch Byte
ARM_tbh,                // Table Branch Halfword
ARM_pli,                // Prepare to load code
ARM_rbit,               // Reverse Bits
ARM_it,                 // If Then
ARM_mls,                // Multiply and Subtract
ARM_sdiv,               // Signed Divide
ARM_udiv,               // Unsigned Divide
ARM_cbz,                // Compare and Branch on Zero
ARM_cbnz,               // Compare and Branch on Non-Zero
ARM_dsb,                // Data Synchronization Barrier
ARM_dmb,                // Data Memory Barrier
ARM_isb,                // Instruction Synchronization Barrier
ARM_dbg,                // Debug Hint
ARM_udf,                // Permanently undefined
ARM_und = ARM_udf,      // for backward compatibility
// missing instructions (not yet decoded)
ARM_rrx,                // Rotate Right with Extend
ARM_enterx,             // Enter ThumbEE state
ARM_leavex,             // Leave ThumbEE state
ARM_chka,               // Check Array
ARM_hb,                 // Handler Branch
ARM_hbl,                // Handler Branch with Link
ARM_hblp,               // Handler Branch with Link and Parameter
ARM_hbp,                // Handler Branch with Parameter
// NEON (Advanced SIMD) and extra VFP instructions
ARM_vaba,               // Vector Absolute Difference and Accumulate
ARM_vabal,              // Vector Absolute Difference and Accumulate Long
ARM_vabd,               // Vector Absolute Difference
ARM_vabdl,              // Vector Absolute Difference Long
ARM_vabs,               // Vector Absolute
ARM_vacge,              // Vector Absolute Compare Greater Than or Equal
ARM_vacgt,              // Vector Absolute Compare Greater Than
ARM_vacle,              // Vector Absolute Compare Less Than or Equal
ARM_vaclt,              // Vector Absolute Compare Less Than
ARM_vadd,               // Vector Add
ARM_vaddhn,             // Vector Add and Narrow, returning High Half
ARM_vaddl,              // Vector Add Long
ARM_vaddw,              // Vector Add Wide
ARM_vand,               // Vector Bitwise AND
ARM_vbic,               // Vector Bitwise Bit Clear
ARM_vbif,               // Vector Bitwise Insert if False
ARM_vbit,               // Vector Bitwise Insert if True
ARM_vbsl,               // Vector Bitwise Select
ARM_vceq,               // Vector Compare Equal
ARM_vcge,               // Vector Compare Greater Than or Equal
ARM_vcgt,               // Vector Compare Greater Than
ARM_vcle,               // Vector Compare Less Than or Equal
ARM_vcls,               // Vector Count Leading Sign Bits
ARM_vclt,               // Vector Compare Less Than
ARM_vclz,               // Vector Count Leading Zeros
ARM_vcmp,               // Vector Compare
ARM_vcmpe,              // Vector Compare (Quiet NaNs trigger Exception)
ARM_vcnt,               // Vector Count Number of Bits
ARM_vcvt,               // Vector Convert
ARM_vcvtr,              // Vector Convert Rounding
ARM_vcvtb,              // Vector Convert Half-Precision Bottom
ARM_vcvtt,              // Vector Convert Half-Precision Top
ARM_vdiv,               // Vector Divide
ARM_vdup,               // Vector Duplicate
ARM_veor,               // Vector Bitwise Exclusive OR
ARM_vext,               // Vector Extract
ARM_vfma,               // Vector Fused Multiply Accumulate
ARM_vfms,               // Vector Fused Multiply Substract
ARM_vfnma,              // Vector Fused Negated Multiply Accumulate
ARM_vfnms,              // Vector Fused Negated Multiply Substract
ARM_vhadd,              // Vector Halving Add
ARM_vhsub,              // Vector Halving Sub
ARM_vld1,               // Vector Load Single Element
ARM_vld2,               // Vector Load Two-Element Structures
ARM_vld3,               // Vector Load Three-Element Structures
ARM_vld4,               // Vector Load Four-Element Structures
ARM_vldm,               // Vector Load Multiple
ARM_vldr,               // Vector Load Register
ARM_vmax,               // Vector Maximum
ARM_vmin,               // Vector Minimum
ARM_vmla,               // Vector Multiply Accumulate
ARM_vmlal,              // Vector Multiply Accumulate Long
ARM_vmls,               // Vector Multiply Subtract
ARM_vmlsl,              // Vector Multiply Subtract Long
ARM_vmov,               // Vector Move
ARM_vmovl,              // Vector Move Long
ARM_vmovn,              // Vector Move and Narrow
ARM_vmrs,               // Move FPSCR to ARM Register
ARM_vmsr,               // Move to FPSCR from ARM Register
ARM_vmul,               // Vector Multiply
ARM_vmull,              // Vector Multiply Long
ARM_vmvn,               // Vector Bitwise NOT
ARM_vneg,               // Vector Negate
ARM_vnmla,              // Vector Multiply Add Negated
ARM_vnmls,              // Vector Multiply Substract Negated
ARM_vnmul,              // Vector Multiply Negated
ARM_vorn,               // Vector Bitwise OR NOT
ARM_vorr,               // Vector Bitwise OR
ARM_vpadal,             // Vector Pairwise Add and Accumulate Long
ARM_vpadd,              // Vector Pairwise Add
ARM_vpaddl,             // Vector Pairwise Add Long
ARM_vpmax,              // Vector Pairwise Maximum
ARM_vpmin,              // Vector Pairwise Minimum
ARM_vpop,               // Vector Pop
ARM_vpush,              // Vector Push
ARM_vqabs,              // Vector Saturating Absolute
ARM_vqadd,              // Vector Saturating Add
ARM_vqdmlal,            // Vector Saturating Doubling Multiply Accumulate Long
ARM_vqdmlsl,            // Vector Saturating Doubling Multiply Subtract Long
ARM_vqdmulh,            // Vector Saturating Doubling Multiply Returning High Half
ARM_vqdmull,            // Vector Saturating Doubling Multiply Long
ARM_vqmovn,             // Vector Saturating Move and Narrow
ARM_vqmovun,            // Vector Saturating Move and Narrow, Unsigned result
ARM_vqneg,              // Vector Saturating Negate
ARM_vqrdmulh,           // Vector Saturating Rounding Doubling Multiply Returning High Half
ARM_vqrshl,             // Vector Saturating Rounding Shift Left
ARM_vqrshrn,            // Vector Saturating Rounding Shift Right, Narrow
ARM_vqrshrun,           // Vector Saturating Rounding Shift Right, Narrow, Unsigned result
ARM_vqshl,              // Vector Saturating Shift Left
ARM_vqshlu,             // Vector Saturating Shift Left, Unsigned result
ARM_vqshrn,             // Vector Saturating Shift Right, Narrow
ARM_vqshrun,            // Vector Saturating Shift Right, Narrow, Unsigned result
ARM_vqsub,              // Vector Saturating Subtract
ARM_vraddhn,            // Vector Rounding Add and Narrow, returning High Half
ARM_vrecpe,             // Vector Reciprocal Estimate
ARM_vrecps,             // Vector Reciprocal Step
ARM_vrev16,             // Vector Reverse in halfwords
ARM_vrev32,             // Vector Reverse in words
ARM_vrev64,             // Vector Reverse in doublewords
ARM_vrhadd,             // Vector Rounding Halving Add
ARM_vrshl,              // Vector Rounding Shift Left
ARM_vrshr,              // Vector Rounding Shift Right
ARM_vrshrn,             // Vector Rounding Shift Right and Narrow
ARM_vrsqrte,            // Vector Reciprocal Square Root Estimate
ARM_vrsqrts,            // Vector Reciprocal Square Root Step
ARM_vrsra,              // Vector Rounding Shift Right and Accumulate
ARM_vrsubhn,            // Vector Rounding Subtract and Narrow, returning High Half
ARM_vshl,               // Vector Shift Left
ARM_vshll,              // Vector Shift Left Long
ARM_vshr,               // Vector Shift Right
ARM_vshrn,              // Vector Shift Right Narrow
ARM_vsli,               // Vector Shift Left and Insert
ARM_vsqrt,              // Vector Square Root
ARM_vsra,               // Vector Shift Right and Accumulate
ARM_vsri,               // Vector Shift Right and Insert
ARM_vst1,               // Vector Store Single Element
ARM_vst2,               // Vector Store Two-Element Structures
ARM_vst3,               // Vector Store Three-Element Structures
ARM_vst4,               // Vector Store Four-Element Structures
ARM_vstm,               // Vector Store Multiple
ARM_vstr,               // Vector Store Register
ARM_vsub,               // Vector Subtract
ARM_vsubhn,             // Vector Subtract and Narrow, returning High Half
ARM_vsubl,              // Vector Subtract Long
ARM_vsubw,              // Vector Subtract Wide
ARM_vswp,               // Vector Swap
ARM_vtbl,               // Vector Table Lookup
ARM_vtbx,               // Vector Table Extension
ARM_vtrn,               // Vector Transpose
ARM_vtst,               // Vector Test Bits
ARM_vuzp,               // Vector Unzip
ARM_vzip,               // Vector Zip
// ARMv7 Hypervisor extensions
ARM_eret,               // Exception Return
ARM_hvc,                // Hypervisor Call
// new ARMv8 instructions for A32 and T32 mode
ARM_lda,                // Load-Acquire Word/Byte/Halfword
ARM_stl,                // Store-Release Word/Byte/Halfword
ARM_ldaex,              // Load-Acquire Exclusive Word/Byte/Halfword
ARM_stlex,              // Store-Release Exclusive Word/Byte/Halfword
ARM_vsel,               // Floating-point Conditional Select
ARM_vmaxnm,             // Vector Maximum Numeric
ARM_vminnm,             // Vector Minimum Numeric
ARM_vcvta,              // Vector Convert Round to Nearest with Ties to Away
ARM_vcvtn,              // Vector Convert Round to Nearest with Ties to Even
ARM_vcvtp,              // Vector Convert Round towards +Infinity
ARM_vcvtm,              // Vector Convert Round towards -Infinity
ARM_vrintx,             // Vector Round to Integral, FPSCR rounding mode and signaling inexactness
ARM_vrintr,             // Vector Round to Integral, FPSCR rounding mode
ARM_vrintz,             // Vector Round to Integral, Round toward Zero
ARM_vrinta,             // Vector Round to Integral, Round to Nearest with Ties to Away
ARM_vrintn,             // Vector Round to Integral, Round to Nearest with Ties to Even
ARM_vrintp,             // Vector Round to Integral, Round towards +Infinity
ARM_vrintm,             // Vector Round to Integral, Round towards -Infinity
ARM_aesd,               // AES single round decryption
ARM_aese,               // AES single round encryption
ARM_aesimc,             // AES inverse mix columns
ARM_aesmc,              // AES mix columns
ARM_sha1c,              // SHA1 hash update accelerator, choose
ARM_sha1m,              // SHA1 hash update accelerator, majority
ARM_sha1p,              // SHA1 hash update accelerator, parity
ARM_sha1h,              // SHA1 hash update accelerator, rotate left by 30
ARM_sha1su0,            // SHA1 schedule update accelerator, first part
ARM_sha1su1,            // SHA1 schedule update accelerator, second part
ARM_sha256h,            // SHA256 hash update accelerator
ARM_sha256h2,           // SHA256 hash update accelerator upper part
ARM_sha256su0,          // SHA256 schedule update accelerator, first part
ARM_sha256su1,          // SHA256 schedule update accelerator, second part
ARM_dcps1,              // Debug Change Processor State to EL1
ARM_dcps2,              // Debug Change Processor State to EL2
ARM_dcps3,              // Debug Change Processor State to EL3
ARM_hlt,                // Halting mode software breakpoint
ARM_sevl,               // Send Event Locally
// ARMv8 AArch64 new instructions
ARM_tbz,                // Test and Branch Zero
ARM_tbnz,               // Test and Branch Non-Zero
ARM_br,                 // Branch To Register
ARM_blr,                // Branch and Link Register
ARM_ldur,               // Load Single Register (unscaled offset)
ARM_stur,               // Store Single Register (unscaled offset)
ARM_ldp,                // Load Pair
ARM_stp,                // Store Pair
ARM_ldnp,               // Load Non-temporal Pair
ARM_stnp,               // Store Non-temporal Pair
ARM_ldtr,               // Load Unprivileged Register
ARM_sttr,               // Store Unprivileged Register
ARM_ldxr,               // Load Exclusive Register
ARM_stxr,               // Store Exclusive Register
ARM_ldxp,               // Load Exclusive Pair
ARM_stxp,               // Store Exclusive Pair
ARM_ldar,               // Load-Acquire Register
ARM_stlr,               // Store-Release Register
ARM_ldaxr,              // Load-Acquire Exclusive Register
ARM_stlxr,              // Store-Release Exclusive Register
ARM_ldaxp,              // Load-Acquire Exclusive Pair
ARM_stlxp,              // Store Exclusive Pair
ARM_prfm,               // Prefetch Memory
ARM_prfum,              // Prefetch Memory (unscaled offset)
ARM_movi,               // Move Immediate
ARM_mvni,               // Move Inverted Immediate
ARM_movz,               // Move with Zero
ARM_movn,               // Move with Not
ARM_movk,               // Move with Keep
ARM_adrp,               // Address of Page
ARM_bfm,                // Bitfield Move
ARM_sbfm,               // Signed Bitfield Move
ARM_ubfm,               // Unsigned Bitfield Move
// ARM_bfi,                // Bitfield Insert
ARM_bfxil,              // Bitfield Extract and Insert Low
ARM_sbfiz,              // Signed Bitfield Insert in Zero
// ARM_sbfx,               // Signed Bitfield Extract
ARM_ubfiz,              // Signed Bitfield Insert in Zero
// ARM_ubfx,               // Unsigned Bitfield Extract
ARM_extr,               // Extract
ARM_sxtw,               // Signed Extend Word
ARM_uxtw,               // Unsigned Extend Word (non-existing insn)
ARM_eon,                // Bitwise exclusive OR NOT
ARM_not,                // Bitwise NOT
ARM_cls,                // Count Leading Sign Bits
ARM_rev32,              // Reverse Bytes in Words
ARM_csel,               // Conditional Select
ARM_csinc,              // Conditional Select Increment
ARM_csinv,              // Conditional Select Invert
ARM_csneg,              // Conditional Select Negate
ARM_cset,               // Conditional Set
ARM_csetm,              // Conditional Set Mask
ARM_cinc,               // Conditional Increment
ARM_cinv,               // Conditional Invert
ARM_cneg,               // Conditional Negate
ARM_ngc,                // Negate with Carry
ARM_ccmn,               // Conditional Compare Negative
ARM_ccmp,               // Conditional Compare
ARM_madd,               // Multiply-Add
ARM_msub,               // Multiply-Subtract
ARM_mneg,               // Multiply-Negate
ARM_smaddl,             // Signed Multiply-Add Long
ARM_smsubl,             // Signed Multiply-Subtract Long
ARM_smnegl,             // Signed Multiply-Negate Long
ARM_smulh,              // Signed Multiply High
ARM_umaddl,             // Unsigned Multiply-Add Long
ARM_umsubl,             // Unsigned Multiply-Subtract Long
ARM_umnegl,             // Unsigned Multiply-Negate Long
ARM_umulh,              // Unsigned Multiply High
ARM_drps,               // Debug Restore Processor State
ARM_sys,                // System Maintenance Operation
ARM_sysl,               // System Maintenance Operation With Result
ARM_ic,                 // Instruction Cache Maintenance
ARM_dc,                 // Data Cache Maintenance
ARM_at,                 // Address Translation
ARM_tlbi,               // TLB Invalidation
ARM_hint,               // Hint instruction
ARM_brk,                // Monitor debug-mode breakpoint
// AArch64 Advanced SIMD
ARM_uaba,               // Unsigned Integer Absolute Difference and Accumulate
ARM_saba,               // Signed Integer Absolute Difference and Accumulate
ARM_uabal,              // Unsigned Integer Absolute Difference and Accumulate Long
ARM_uabal2,             // Unsigned Integer Absolute Difference and Accumulate Long (Second Part)
ARM_sabal,              // Signed Integer Absolute Difference and Accumulate Long
ARM_sabal2,             // Signed Integer Absolute Difference and Accumulate Long (Second Part)
ARM_uabd,               // Unsigned Integer Absolute Difference
ARM_sabd,               // Signed Integer Absolute Difference
ARM_fabd,               // Floating-point Absolute Difference
ARM_uabdl,              // Unsigned Integer Absolute Difference Long
ARM_uabdl2,             // Unsigned Integer Absolute Difference Long (Second Part)
ARM_sabdl,              // Signed Integer Absolute Difference Long
ARM_sabdl2,             // Signed Integer Absolute Difference Long (Second Part)
ARM_abs,                // Integer Absolute Value
ARM_fabs,               // Floating-point Absolute Value
ARM_facge,              // Floating-point Absolute Compare Greater Than or Equal
ARM_facgt,              // Floating-point Absolute Compare Greater Than
ARM_facle,              // Floating-point Absolute Compare Less Than or Equal
ARM_faclt,              // Floating-point Absolute Compare Less Than
ARM_fadd,               // Floating-point Add
ARM_addhn,              // Integer Vector Add and Narrow High Half
ARM_addhn2,             // Integer Vector Add and Narrow High Half (second part)
ARM_uaddl,              // Unsigned Integer Add Long
ARM_uaddl2,             // Unsigned Integer Add Long (second part)
ARM_saddl,              // Signed Integer Add Long
ARM_saddl2,             // Signed Integer Add Long (second part)
ARM_uaddw,              // Unsigned Integer Add Wide
ARM_uaddw2,             // Unsigned Integer Add Wide (second part)
ARM_saddw,              // Signed Integer Add Wide
ARM_saddw2,             // Signed Integer Add Wide (second part)
ARM_bif,                // Bitwise Vector Insert if False
ARM_bit,                // Bitwise Vector Insert if True
ARM_bsl,                // Bitwise Vector Select
ARM_cmeq,               // Ingeger Vector Compare Equal
ARM_fcmeq,              // Floating-point Vector Compare Equal
ARM_cmhs,               // Unsigned Compare Greater Than or Equal
ARM_cmge,               // Signed Compare Greater Than or Equal
ARM_fcmge,              // Floating-point Compare Greater Than or Equal
ARM_cmhi,               // Unsigned Compare Greater Than
ARM_cmgt,               // Signed Compare Greater Than
ARM_fcmgt,              // Floating-point Compare Greater Than
ARM_cmls,               // Unsigned Compare Less Than or Equal
ARM_cmle,               // Signed Compare Less Than or Equal
ARM_fcmle,              // Floating-point Compare Less Than or Equal
ARM_cmlo,               // Unsigned Compare Less Than
ARM_cmlt,               // Signed Compare Less Than
ARM_fcmlt,              // Floating-point Compare Less Than
ARM_fcmp,               // Floating-point Compare
ARM_fcmpe,              // Floating-point Signaling Compare
ARM_fccmp,              // Floating-point Conditional Quiet Compare
ARM_fccmpe,             // Floating-point Conditional Signaling Compare
ARM_fcsel,              // Floating-point Conditional Select
ARM_cnt,                // Count Non-zero Bits
ARM_fcvt,               // Floating-point convert precision (scalar)
ARM_fcvtzs,             // Convert Floating-point to Signed Integer (Round to Zero)
ARM_fcvtas,             // Convert Floating-point to Signed Integer (Round to Nearest, Ties to Away)
ARM_fcvtns,             // Convert Floating-point to Signed Integer (Round to Nearest, Ties to Even)
ARM_fcvtps,             // Convert Floating-point to Signed Integer (Round towards +Infinity)
ARM_fcvtms,             // Convert Floating-point to Signed Integer (Round towards -Infinity)
ARM_fcvtzu,             // Convert Floating-point to Unsigned Integer (Round to Zero)
ARM_fcvtau,             // Convert Floating-point to Unsigned Integer (Round to Nearest, Ties to Away)
ARM_fcvtnu,             // Convert Floating-point to Unsigned Integer (Round to Nearest, Ties to Even)
ARM_fcvtpu,             // Convert Floating-point to Unsigned Integer (Round towards +Infinity)
ARM_fcvtmu,             // Convert Floating-point to Unsigned Integer (Round towards -Infinity)
ARM_ucvtf,              // Convert Unsigned Integer to Floating-point
ARM_scvtf,              // Convert Signed Integer to Floating-point
ARM_fcvtn,              // Floating-point Convert Precision, Narrow
ARM_fcvtn2,             // Floating-point Convert Precision, Narrow (second part)
ARM_fcvtl,              // Floating-point Convert Precision, Long
ARM_fcvtl2,             // Floating-point Convert Precision, Long (second part)
ARM_fcvtxn,             // Floating-point Convert Precision, Narrow (Round to Odd)
ARM_fcvtxn2,            // Floating-point Convert Precision, Narrow (Round to Odd) (second part)
ARM_frinta,             // Floating-point Round to Integral (Round to Nearest, Ties to Away)
ARM_frinti,             // Floating-point Round to Integral (using FPCR rounding mode)
ARM_frintm,             // Floating-point Round to Integral (Round towards -Infinity)
ARM_frintn,             // Floating-point Round to Integral (Round to Nearest, Ties to Even)
ARM_frintp,             // Floating-point Round to Integral (Round towards +Infinity)
ARM_frintx,             // Floating-point Round to Integral (using FPCR rounding mode, with exactness test)
ARM_frintz,             // Floating-point Round to Integral (Round towards Zero)
ARM_fmadd,              // Floating-point scalar fused multiply-add
ARM_fmsub,              // Floating-point scalar fused multiply-subtract
ARM_fnmadd,             // Floating-point scalar negated fused multiply-add
ARM_fnmsub,             // Floating-point scalar negated fused multiply-subtract
ARM_fdiv,               // Floating-point Divide
ARM_dup,                // Duplicate Single Element to All Elements
ARM_ins,                // Insert Single Element in Another Element
ARM_ext,                // Bitwise Extract
ARM_uhadd,              // Unsigned Integer Halving Add
ARM_shadd,              // Signed Integer Halving Add
ARM_uhsub,              // Unsigned Integer Halving Subtract
ARM_shsub,              // Signed Integer Halving Subtract
ARM_ld1,                // Vector Load Single Element
ARM_ld2,                // Vector Load Two-Element Structures
ARM_ld3,                // Vector Load Three-Element Structures
ARM_ld4,                // Vector Load Four-Element Structures
ARM_ld1r,               // Vector Load Single Element and Replicate
ARM_ld2r,               // Vector Load Two-Element Structures and Replicate
ARM_ld3r,               // Vector Load Three-Element Structures and Replicate
ARM_ld4r,               // Vector Load Four-Element Structures and Replicate
ARM_umax,               // Unsigned Integer Maximum
ARM_smax,               // Signed Integer Maximum
ARM_fmax,               // Floating-point Maximum
ARM_fmaxnm,             // Floating-point maxNum()
ARM_umin,               // Unsigned Integer Minimum
ARM_smin,               // Signed Integer Minimum
ARM_fmin,               // Floating-point Minimum
ARM_fminnm,              // Floating-point minNum()
ARM_fmla,               // Fused Multiply-Add
ARM_umlal2,             // Unsigned Integer Multiply-Add Long (second part)
ARM_smlal2,             // Signed Integer Multiply-Add Long (second part)
ARM_fmls,               // Fused Multiply-Subtract
ARM_umlsl,              // Unsigned Integer Multiply-Subtract Long
ARM_umlsl2,             // Unsigned Integer Multiply-Subtract Long (second part)
ARM_smlsl,              // Signed Integer Multiply-Subtract Long
ARM_smlsl2,             // Signed Integer Multiply-Subtract Long (second part)
ARM_umov,               // Unsigned Integer Move
ARM_smov,               // Signed Integer Move
ARM_fmov,               // Floating-point Move
ARM_uxtl,               // Unsigned Integer Vector Lengthen
ARM_uxtl2,              // Unsigned Integer Vector Lengthen (second part)
ARM_sxtl,               // Signed Integer Vector Lengthen
ARM_sxtl2,              // Signed Integer Vector Lengthen (second part)
ARM_xtn,                // Integer Vector Narrow
ARM_xtn2,               // Integer Vector Narrow (second part)
ARM_fmul,               // Floating-point Vector Multiply
ARM_pmul,               // Polynomial Vector Multiply
ARM_fmulx,              // Floating-point Multiply Extended
ARM_fnmul,              // Floating-point Multiply-Negate
ARM_umull2,             // Unsigned Integer Vector Multiply Long (second part)
ARM_smull2,             // Signed Integer Vector Multiply Long (second part)
ARM_pmull,              // Polynomial Vector Multiply Long
ARM_pmull2,             // Polynomial Vector Multiply Long (second part)
ARM_fneg,               // Floating-point Negate
ARM_uadalp,             // Unsigned Integer Vector Add and Accumulate Long Pair
ARM_sadalp,             // Signed Integer Vector Add and Accumulate Long Pair
ARM_addp,               // Integer Vector Add Pair
ARM_faddp,              // Floating-point Vector Add Pair
ARM_uaddlp,             // Unsigned Integer Vector Add Long Pair
ARM_saddlp,             // Signed Integer Vector Add Long Pair
ARM_umaxp,              // Unsigned Integer Maximum Pair
ARM_smaxp,              // Signed Integer Maximum Pair
ARM_fmaxp,              // Floating-point Maximum Pair
ARM_fmaxnmp,            // Floating-point maxNum Pair
ARM_uminp,              // Unsigned Integer Minimum Pair
ARM_sminp,              // Signed Integer Minimum Pair
ARM_fminp,              // Floating-point Minimum Pair
ARM_fminnmp,            // Floating-point minNum Pair
ARM_sqabs,              // Signed Integer Saturating Absolute
ARM_uqadd,              // Unsigned Integer Saturating Add
ARM_sqadd,              // Signed Integer Saturating Add
ARM_suqadd,             // Signed Integer Saturating Accumulate of Unsigned Values
ARM_usqadd,             // Unsigned Integer Saturating Accumulate of Signed Values
ARM_sqdmlal,            // Signed Integer Saturating Doubling Multiply Add Long
ARM_sqdmlal2,           // Signed Integer Saturating Doubling Multiply Add Long (second part)
ARM_sqdmlsl,            // Signed Integer Saturating Doubling Multiply Subtract Long
ARM_sqdmlsl2,           // Signed Integer Saturating Doubling Multiply Subtract Long (second part)
ARM_sqdmulh,            // Signed Integer Saturating Doubling Multiply Returning High Half
ARM_sqdmull,            // Signed Integer Saturating Doubling Multiply Long
ARM_sqdmull2,           // Signed Integer Saturating Doubling Multiply Long (second part)
ARM_uqxtn,              // Unsigned Integer Saturating Vector Narrow
ARM_uqxtn2,             // Unsigned Integer Saturating Vector Narrow (second part)
ARM_sqxtn,              // Signed Integer Saturating Vector Narrow
ARM_sqxtn2,             // Signed Integer Saturating Vector Narrow (second part)
ARM_sqxtun,             // Signed Integer Saturating Vector and Unsigned Narrow
ARM_sqxtun2,            // Signed Integer Saturating Vector and Unsigned Narrow (second part)
ARM_sqneg,              // Signed Integer Saturating Negate
ARM_sqrdmulh,           // Signed Integer Saturating Rounding Doubling Multiply Returning High Half
ARM_uqrshl,             // Unsigned Integer Saturating Rounding Shift Left
ARM_sqrshl,             // Signed Integer Saturating Rounding Shift Left
ARM_uqrshrn,            // Unsigned Integer Saturating Rounding Shift Right, Narrow
ARM_uqrshrn2,           // Unsigned Integer Saturating Rounding Shift Right, Narrow (second part)
ARM_sqrshrn,            // Signed Integer Saturating Rounding Shift Right, Narrow
ARM_sqrshrn2,           // Signed Integer Saturating Rounding Shift Right, Narrow (second part)
ARM_sqrshrun,           // Signed Integer Saturating Rounding Shift Right, Narrow, Unsigned result
ARM_sqrshrun2,          // Signed Integer Saturating Rounding Shift Right, Narrow, Unsigned result (second part)
ARM_uqshl,              // Unsigned Integer Saturating Shift Left
ARM_sqshl,              // Signed Integer Saturating Shift Left
ARM_sqshlu,             // Signed Integer Saturating Shift Left, Unsigned result
ARM_uqshrn,             // Unsigned Integer Saturating Shift Right, Narrow
ARM_uqshrn2,            // Unsigned Integer Saturating Shift Right, Narrow (second part)
ARM_sqshrn,             // Signed Integer Saturating Shift Right, Narrow
ARM_sqshrn2,            // Signed Integer Saturating Shift Right, Narrow (second part)
ARM_sqshrun,            // Signed Integer Saturating Shift Right, Narrow, Unsigned result
ARM_sqshrun2,           // Signed Integer Saturating Shift Right, Narrow, Unsigned result (second part)
ARM_uqsub,              // Unsigned Integer Saturating Subtract
ARM_sqsub,              // Signed Integer Saturating Subtract
ARM_raddhn,             // Integer Rounding Add and Narrow, returning High Half
ARM_raddhn2,            // Integer Rounding Add and Narrow, returning High Half (second part)
ARM_urecpe,             // Unsigned Integer Reciprocal Estimate
ARM_frecpe,             // Floating-point Reciprocal Estimate
ARM_frecps,             // Floating-point Reciprocal Step
ARM_frecpx,             // Floating-point Reciprocal Exponent
ARM_rev64,              // Reverse doublewords
ARM_urhadd,             // Unsigned Integer Rounding Halving Add
ARM_srhadd,             // Signed Integer Rounding Halving Add
ARM_urshl,              // Unsigned Integer Rounding Shift Left
ARM_srshl,              // Signed Integer Rounding Shift Left
ARM_urshr,              // Unsigned Integer Rounding Shift Right
ARM_srshr,              // Signed Integer Rounding Shift Right
ARM_rshrn,              // Integer Rounding Shift Right and Narrow
ARM_rshrn2,             // Integer Rounding Shift Right and Narrow (second part)
ARM_ursqrte,            // Unsigned Integer Reciprocal Square Root Estimate
ARM_frsqrte,            // Floating-point Reciprocal Square Root Estimate
ARM_frsqrts,            // Floating-point Reciprocal Square Root Step
ARM_ursra,              // Unsigned Integer Rounding Shift Right and Accumulate
ARM_srsra,              // Signed Integer Rounding Shift Right and Accumulate
ARM_rsubhn,             // Integer Subtract and Narrow, returning High Half
ARM_rsubhn2,            // Integer Subtract and Narrow, returning High Half (second part)
ARM_ushl,               // Unsigned Integer Shift Left
ARM_sshl,               // Signed Integer Shift Left
ARM_ushll,              // Unsigned Integer Shift Left Long
ARM_ushll2,             // Unsigned Integer Shift Left Long (second part)
ARM_sshll,              // Signed Integer Shift Left Long
ARM_sshll2,             // Signed Integer Shift Left Long (second part)
ARM_ushr,               // Unsigned Integer Shift Right
ARM_sshr,               // Signed Integer Shift Right
ARM_shrn,               // Integer Shift Right Narrow
ARM_shrn2,              // Integer Shift Right Narrow (second part)
ARM_shl,                // Shift Left
ARM_shll,               // Shift Left Long
ARM_shll2,              // Shift Left Long (second part)
ARM_sli,                // Integer Vector Shift Left and Insert
ARM_fsqrt,              // Floating-point Square Root
ARM_usra,               // Unsigned Integer Shift Right and Accumulate
ARM_ssra,               // Signed Integer Shift Right and Accumulate
ARM_sri,                // Integer Shift Right and Insert
ARM_st1,                // Vector Store Single Element
ARM_st2,                // Vector Store Two-Element Structures
ARM_st3,                // Vector Store Three-Element Structures
ARM_st4,                // Vector Store Four-Element Structures
ARM_fsub,               // Floating-point Subtract
ARM_subhn,              // Integer Subtract and Narrow, returning High Half
ARM_subhn2,             // Integer Subtract and Narrow, returning High Half (second part)
ARM_usubl,              // Unsigned Integer Subtract Long
ARM_usubl2,             // Unsigned Integer Subtract Long (second part)
ARM_ssubl,              // Signed Integer Subtract Long
ARM_ssubl2,             // Signed Integer Subtract Long (second part)
ARM_usubw,              // Unsigned Integer Subtract Wide
ARM_usubw2,             // Unsigned Integer Subtract Wide (second part)
ARM_ssubw,              // Signed Integer Subtract Wide
ARM_ssubw2,             // Signed Integer Subtract Wide (second part)
ARM_tbl,                // Vector Table Lookup
ARM_tbx,                // Vector Table Extension
ARM_trn1,               // Vector Element Transpose (primary)
ARM_trn2,               // Vector Element Transpose (secondary)
ARM_cmtst,              // Integer Compare Mask Bitwise Test
ARM_uzp1,               // Vector Element Unzip (primary)
ARM_uzp2,               // Vector Element Unzip (secondary)
ARM_zip1,               // Vector Element Zip (primary)
ARM_zip2,               // Vector Element Zip (secondary)
ARM_addv,               // Integer Sum Elements in Vector
ARM_uaddlv,             // Unsigned Integer Sum Elements in Vector Long
ARM_saddlv,             // Signed Integer Sum Elements in Vector Long
ARM_umaxv,              // Unsigned Integer Max Element in Vector
ARM_smaxv,              // Signed Integer Max Element in Vector
ARM_fmaxv,              // Floating-point Max Element in Vector
ARM_fmaxnmv,            // Floating-point maxNum Element in Vector
ARM_uminv,              // Unsigned Integer Min Element in Vector
ARM_sminv,              // Signed Integer Min Element in Vector
ARM_fminv,              // Floating-point Min Element in Vector
ARM_fminnmv,            // Floating-point minNum Element in Vector
// atomic operations (ARMv8.1/ARMv8.3)
// ARM_swp,              // Swap value with memory, No memory ordering
ARM_swpl,               // Swap value with memory, Release
ARM_swpa,               // Swap value with memory, Acquire
ARM_swpal,              // Swap value with memory, Acquire and release
ARM_ldapr,              // Load-Acquire RCpc Register
ARM_ldadd,             // Atomic add on value in memory (return initial value), No memory ordering
ARM_ldaddl,            // Atomic add on value in memory (return initial value), Release
ARM_ldadda,            // Atomic add on value in memory (return initial value), Acquire
ARM_ldaddal,           // Atomic add on value in memory (return initial value), Acquire and release
ARM_stadd,             // Atomic add on value in memory (no return), No memory ordering
ARM_staddl,            // Atomic add on value in memory (no return), Release
ARM_ldclr,             // Atomic bit clear on value in memory (return initial value), No memory ordering
ARM_ldclrl,            // Atomic bit clear on value in memory (return initial value), Release
ARM_ldclra,            // Atomic bit clear on value in memory (return initial value), Acquire
ARM_ldclral,           // Atomic bit clear on value in memory (return initial value), Acquire and release
ARM_stclr,             // Atomic bit clear on value in memory (no return), No memory ordering
ARM_stclrl,            // Atomic bit clear on value in memory (no return), Release
ARM_ldeor,             // Atomic exclusive OR on value in memory (return initial value), No memory ordering
ARM_ldeorl,            // Atomic exclusive OR on value in memory (return initial value), Release
ARM_ldeora,            // Atomic exclusive OR on value in memory (return initial value), Acquire
ARM_ldeoral,           // Atomic exclusive OR on value in memory (return initial value), Acquire and release
ARM_steor,             // Atomic exclusive OR on value in memory (no return), No memory ordering
ARM_steorl,            // Atomic exclusive OR on value in memory (no return), Release
ARM_ldset,             // Atomic bit set on value in memory (return initial value), No memory ordering
ARM_ldsetl,            // Atomic bit set on value in memory (return initial value), Release
ARM_ldseta,            // Atomic bit set on value in memory (return initial value), Acquire
ARM_ldsetal,           // Atomic bit set on value in memory (return initial value), Acquire and release
ARM_stset,             // Atomic bit set on value in memory (no return), No memory ordering
ARM_stsetl,            // Atomic bit set on value in memory (no return), Release
ARM_ldsmax,            // Atomic signed maximum  on value in memory (return initial value), No memory ordering
ARM_ldsmaxl,           // Atomic signed maximum  on value in memory (return initial value), Release
ARM_ldsmaxa,           // Atomic signed maximum  on value in memory (return initial value), Acquire
ARM_ldsmaxal,          // Atomic signed maximum  on value in memory (return initial value), Acquire and release
ARM_stsmax,            // Atomic signed maximum  on value in memory (no return), No memory ordering
ARM_stsmaxl,            // Atomic signed maximum  on value in memory (no return), Release
ARM_ldsmin,            // Atomic signed minimum  on value in memory (return initial value), No memory ordering
ARM_ldsminl,           // Atomic signed minimum  on value in memory (return initial value), Release
ARM_ldsmina,           // Atomic signed minimum  on value in memory (return initial value), Acquire
ARM_ldsminal,          // Atomic signed minimum  on value in memory (return initial value), Acquire and release
ARM_stsmin,            // Atomic signed minimum  on value in memory (no return), No memory ordering
ARM_stsminl,            // Atomic signed minimum  on value in memory (no return), Release
ARM_ldumax,            // Atomic unsigned maximum  on value in memory (return initial value), No memory ordering
ARM_ldumaxl,           // Atomic unsigned maximum  on value in memory (return initial value), Release
ARM_ldumaxa,           // Atomic unsigned maximum  on value in memory (return initial value), Acquire
ARM_ldumaxal,          // Atomic unsigned maximum  on value in memory (return initial value), Acquire and release
ARM_stumax,            // Atomic unsigned maximum  on value in memory (no return), No memory ordering
ARM_stumaxl,            // Atomic unsigned maximum  on value in memory (no return), Release
ARM_ldumin,            // Atomic unsigned minimum  on value in memory (return initial value), No memory ordering
ARM_lduminl,           // Atomic unsigned minimum  on value in memory (return initial value), Release
ARM_ldumina,           // Atomic unsigned minimum  on value in memory (return initial value), Acquire
ARM_lduminal,          // Atomic unsigned minimum  on value in memory (return initial value), Acquire and release
ARM_stumin,            // Atomic unsigned minimum  on value in memory (no return), No memory ordering
ARM_stuminl,            // Atomic unsigned minimum  on value in memory (no return), Release
// Compare and Swap (ARMv8.1)
ARM_cas,            // Compare and Swap , No memory ordering
ARM_casl,           // Compare and Swap, Release
ARM_casa,           // Compare and Swap, Acquire
ARM_casal,          // Compare and Swap, Acquire and release
ARM_casp,            // Compare and Swap Pair, No memory ordering
ARM_caspl,           // Compare and Swap Pair, Release
ARM_caspa,           // Compare and Swap Pair, Acquire
ARM_caspal,          // Compare and Swap Pair, Acquire and release
ARM_ldlar,           // Load LOAcquire Register
ARM_stllr,           // Store LORelease Register
ARM_sqrdmlah,        // Signed Saturating Rounding Doubling Multiply Accumulate
ARM_sqrdmlsh,        // Signed Saturating Rounding Doubling Multiply Subtract
// Pointer authentication (ARMv8.3)
// only completely new instructions are included;
// authenticated variations of old ones are represented by instruction flags (see arm.hpp)
ARM_pac,             // Pointer Authentication Code for Data/Instruction address/generic
ARM_aut,             // Authenticate Data/Instruction address
ARM_xpac,            // Strip Pointer Authentication Code
// ARM insns for the legacy assembler (2 operands)
ARM_ldrd2,           // Load pair of registers
ARM_strd2,           // Store pair of registers
// CRC32 (optional in 8.0, mandatory since 8.1)
ARM_crc32,           // CRC32 using polynomial 0x04C11DB7
ARM_crc32c,          // CRC32 using polynomial 0x1EDC6F41
// Armv8-M Security Extension (TrustZone for Armv8-M)
ARM_tt, // Test Target (query the Security state and access permissions of a memory location)
ARM_tta, // Test Target Alternate Domain (query the Security state and access permissions of a memory location for a Non-secure access)
ARM_sg, // Secure Gateway
ARM_vlldm, // Floating-point Lazy Load Multiple
ARM_vlstm, // Floating-point Lazy Store Multiple
// MP Extension instructions
ARM_pldw, // Preload Data for write
// ARMv8.1-RDMA (AArh32)
ARM_vqrdmlah, // Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.
              // Vector Saturating Rounding Doubling Multiply Accumulate
ARM_vqrdmlsh, // Vector Saturating Rounding Doubling Multiply Subtract Returning High Half
// ARMv8.2-FP16 (AArch32)
ARM_vmovx, // Vector Move extraction
ARM_vins,  // Vector move Insertion.
// ARMv8.3-JSConv (AArch32)
ARM_vjcvt,    // Javascript Convert to signed fixed-point, rounding toward Zero
// ARMv8.3-JSConv (A64)
ARM_fjcvtzs, // Javascript Convert to signed fixed-point, rounding toward Zero
/*
// ARMv8.3-CompNum, SIMD complex number support
ARM_fcadd, // Floating-point complex add
ARM_fcmla, // Floating-point complex multiply accumulate
*/
// ARMv8.4-RCPC
ARM_ldapur,             // Load-Acquire RCpc Register (unscaled offset)
ARM_stlur,              // Store-Release Register (unscaled offset)
// ARMv8.4
ARM_cfinv,              // Invert Carry Flag
ARM_rmif,               // Rotate value and mask into flags
ARM_setf8,              // set flags from value (8-bit)
ARM_setf16,             // set flags from value (16-bit)
ARM_xaflag,             // Convert floating-point condition flags to ARM format
ARM_axflag,             // Convert floating-point condition flags from ARM to external format.
// ARMv8.5
ARM_addg,               // Add with Tag
ARM_subg,               // Subtract with Tag
ARM_subp,               // Subtract Pointer
ARM_cmpp,               // Compare with Tag
ARM_irg,                // Insert Random Tag
ARM_gmi,                // Tag Mask Insert
ARM_stg,                // Store Allocation Tag
ARM_stzg,               // Store Allocation Tag, Zeroing
ARM_stzgm,              // Store Tag and Zero Multiple
ARM_st2g,               // Store Allocation Tags
ARM_stz2g,              // Store Allocation Tags, Zeroing
ARM_stgm,               // Store Tag Multiple
ARM_stgp,               // Store Allocation Tag and Pair of registers
ARM_ldg,                // Load Allocation Tag
ARM_ldgm,               // Load Tag Multiple
ARM_bti,                // Branch Target Identification
ARM_sb,                 // Speculation Barrier
ARM_ssbb,               // Speculative Store Bypass Barrier
ARM_pssbb,              // Physical Speculative Store Bypass Barrier
//
ARM_frint32x,             // Floating-point Round to 32-bit Integer, using current rounding mode
ARM_frint32z,             // Floating-point Round to 32-bit Integer toward Zero
ARM_frint64x,             // Floating-point Round to 32-bit Integer, using current rounding mode
ARM_frint64z,             // Floating-point Round to 32-bit Integer toward Zero
// ARMv8.2-SHA3 (AArch64)
ARM_bcax, // Bit Clear and exclusive-OR
ARM_eor3, // Three-way Exclusive-OR
ARM_rax1, // Rotate and Exclusive-OR
ARM_xar,  // Exclusive-OR and Rotate
// ARMv8.2-SHA512 (AArch64)
ARM_sha512h,   // SHA512 Hash update part 1
ARM_sha512h2,  // SHA512 Hash update part 2
ARM_sha512su0, // SHA512 Schedule Update 0
ARM_sha512su1, // SHA512 Schedule Update 1
// ARMv8.2-SM3 (AArch64)
ARM_sm3partw1,
ARM_sm3partw2,
ARM_sm3ss1,
ARM_sm3tt1a,
ARM_sm3tt1b,
ARM_sm3tt2a,
ARM_sm3tt2b,
// ARMv8.2-SM4 (AArch64)
ARM_sm4e,
ARM_sm4ekey,
// ARMv8.6-I8MM (AArch64)
ARM_sudot,
ARM_ummla,
ARM_usdot,
ARM_usmmla,
// ARMv8.6-DotProd (AArch64)
ARM_sdot,
ARM_udot,
// ARMv8.2-FHM (AArch64)
ARM_fmlal,
ARM_fmlal2,
ARM_fmlsl,
ARM_fmlsl2,
// ARMv8.6-BF16 (AArch64)
ARM_bfmmla,
ARM_bfmlalb,
ARM_bfmlalt,
ARM_bfdot,
ARM_bfcvtn,
ARM_bfcvtn2,
ARM_bfcvt,
// Apple custom instructions
ARM_trap,                 // Undefined opcode used for debugging
ARM_trap2,                // Undefined opcode used for debugging
ARM_genter,               // Enter guarded execution mode
ARM_gexit,                // Exit guarded execution mode
ARM_wkdmc,                // Compress memory page
ARM_wkdmd,                // Decompress memory page
ARM_sdsb,                 // Strong data synchronization barrier
ARM_amx,                  // AMX instruction
ARM_mul53lo,              // Multiply 2 53-bit pairs and store low 53 bits
ARM_mul53hi,              // Multiply 2 53-bit pairs and store high 53 bits
// ARMv8.1-M MVE
ARM_vbrsr,                // Vector Bit Reverse and Shift Right
ARM_vcmul,                // Vector Complex Multiply
ARM_vfmas,                // Vector Fused Multiply Accumulate Scalar
ARM_vmaxa,                // Vector Maximum Absolute
ARM_vmaxnma,              // Vector Maximum Absolute (floating-point)
ARM_vmina,                // Vector Minimum Absolute
ARM_vminnma,              // Vector Minimum Absolute (floating-point)
ARM_vmlas,                // Vector Multiply Accumulate Scalar
ARM_vmovnb,               // Vector Move and Narrow Bottom
ARM_vmovnt,               // Vector Move and Narrow Top
ARM_vmulh,                // Vector Multiply Returning High Half
ARM_vrmulh,               // Vector Rounding Multiply Returning High Half
ARM_vmullb,               // Vector Multiply Long Bottom
ARM_vmullt,               // Vector Multiply Long Top
ARM_vqdmladh,             // Vector Saturating Doubling Multiply Add Dual Returning High Half
ARM_vqdmladhX,            // Vector Saturating Doubling Multiply Add Dual Returning High Half (exchange)
ARM_vqrdmladh,            // Vector Saturating Rounding Doubling Multiply Add Dual Returning High Half
ARM_vqrdmladhX,           // Vector Saturating Rounding Doubling Multiply Add Dual Returning High Half (exchange)
ARM_vqdmlah,              // Vector Saturating Doubling Multiply Accumulate
ARM_vqdmlash,             // Vector Saturating Doubling Multiply Accumulate Scalar High Half
ARM_vqrdmlash,            // Vector Saturating Rounding Doubling Multiply Accumulate Scalar High Half
ARM_vqdmlsdh,             // Vector Saturating Doubling Multiply Subtract Dual Returning High Half
ARM_vqdmlsdhX,            // Vector Saturating Doubling Multiply Subtract Dual Returning High Half (exchange)
ARM_vqrdmlsdh,            // Vector Saturating Rounding Doubling Multiply Subtract Dual Returning High Half
ARM_vqrdmlsdhX,           // Vector Saturating Rounding Doubling Multiply Subtract Dual Returning High Half (exchange)
ARM_vqmovnb,              // Vector Saturating Move and Narrow Bottom
ARM_vqmovnt,              // Vector Saturating Move and Narrow Top
ARM_vqmovunb,             // Vector Saturating Move Unsigned and Narrow Bottom
ARM_vqmovunt,             // Vector Saturating Move Unsigned and Narrow Top
ARM_vshllb,               // Vector Shift Left Long Bottom
ARM_vshllt,               // Vector Shift Left Long Top
ARM_vmladav,              // Vector Multiply Add Dual Accumulate Across Vector
ARM_vmladavX,             // Vector Multiply Add Dual Accumulate Across Vector (exchange)
ARM_vmladavA,             // Vector Multiply Add Dual Accumulate Across Vector (accumulate)
ARM_vmladavAX,            // Vector Multiply Add Dual Accumulate Across Vector (accumulate, exchange)
ARM_vmlsdav,              // Vector Multiply Subtract Dual Accumulate Across Vector
ARM_vmlsdavX,             // Vector Multiply Subtract Dual Accumulate Across Vector (exchange)
ARM_vmlsdavA,             // Vector Multiply Subtract Dual Accumulate Across Vector (accumulate)
ARM_vmlsdavAX,            // Vector Multiply Subtract Dual Accumulate Across Vector (accumulate, exchange)
ARM_vmlaldav,             // Vector Multiply Add Long Dual Accumulate Across Vector
ARM_vmlaldavX,            // Vector Multiply Add Long Dual Accumulate Across Vector (exchange)
ARM_vmlaldavA,            // Vector Multiply Add Long Dual Accumulate Across Vector (accumulate)
ARM_vmlaldavAX,           // Vector Multiply Add Long Dual Accumulate Across Vector (accumulate, exchange)
ARM_vmlsldav,             // Vector Multiply Subtract Long Dual Accumulate Across Vector
ARM_vmlsldavX,            // Vector Multiply Subtract Long Dual Accumulate Across Vector (exchange)
ARM_vmlsldavA,            // Vector Multiply Subtract Long Dual Accumulate Across Vector (accumulate)
ARM_vmlsldavAX,           // Vector Multiply Subtract Long Dual Accumulate Across Vector (accumulate, exchange)
ARM_vrmlsldavh,           // Vector Rounding Multiply Subtract Long Dual Accumulate Across Vector Returning High 64 bits
ARM_vrmlsldavhX,          // Vector Rounding Multiply Subtract Long Dual Accumulate Across Vector Returning High 64 bits (exchange)
ARM_vrmlsldavhA,          // Vector Rounding Multiply Subtract Long Dual Accumulate Across Vector Returning High 64 bits (accumulate)
ARM_vrmlsldavhAX,         // Vector Rounding Multiply Subtract Long Dual Accumulate Across Vector Returning High 64 bits (accumulate, exchange)
ARM_vidup,                // Vector Increment and Duplicate
ARM_vddup,                // Vector Decrement and Duplicate
ARM_viwdup,               // Vector Increment with Wrap and Duplicate
ARM_vdwdup,               // Vector Decrement with Wrap and Duplicate
ARM_vhcadd,               // Vector Halving Complex Add with Rotate
ARM_vcadd,                // Vector Complex Add with Rotate
ARM_vadc,                 // Whole Vector Add With Carry
ARM_vadcI,                // Whole Vector Add With Carry (initial carry is 1)
ARM_sbdc,                 // Whole Vector Subtract With Carry
ARM_vsbcI,                // Whole Vector Subtract With Carry (initial carry is 1)
ARM_vqdmullb,             // Vector Multiply Long Bottom
ARM_vqdmullt,             // Vector Multiply Long Top
ARM_vpsel,                // Vector Predicated Select
ARM_vcmpv,                // Vector Compare (vector)
ARM_vpt,                  // Vector Predicate Then
ARM_vpnot,                // Vector Predicate NOT
ARM_vpst,                 // Vector Predicate Set Then
ARM_vmaxv,                // Vector Maximum Across Vector
ARM_vmaxav,               // Vector Maximum Absolute Across Vector
ARM_vminv,                // Vector Minimum Across Vector
ARM_vminav,               // Vector Minimum Absolute Across Vector
ARM_vmaxnmv,              // Vector Maximum Across Vector (floating-point)
ARM_vmaxnmav,             // Vector Maximum Absolute Across Vector (floating-point)
ARM_vminnmv,              // Vector Minimum Across Vector (floating-point)
ARM_vminnmav,             // Vector Minimum Absolute Across Vector (floating-point)
ARM_vqshrnb,              // Vector Saturating Shift Right and Narrow Bottom
ARM_vqshrnt,              // Vector Saturating Shift Right and Narrow Top
ARM_vqrshrnb,             // Vector Saturating Rounding Shift Right and Narrow Bottom
ARM_vqrshrnt,             // Vector Saturating Rounding Shift Right and Narrow Top
ARM_vqshrunb,             // Vector Saturating Shift Right Unsigned and Narrow Bottom
ARM_vqshrunt,             // Vector Saturating Shift Right Unsigned and Narrow Top
ARM_vqrshrunb,            // Vector Saturating Rounding Shift Right Unsigned and Narrow Bottom
ARM_vqrshrunt,            // Vector Saturating Rounding Shift Right Unsigned and Narrow Top
ARM_vshrnb,               // Vector Shift Right and Narrow Bottom
ARM_vshrnt,               // Vector Shift Right and Narrow Top
ARM_vrshrnb,              // Vector Rounding Shift Right and Narrow Bottom
ARM_vrshrnt,              // Vector Rounding Shift Right and Narrow Top
ARM_vrmlaldavh,           // Vector Rounding Multiply Add Long Dual Accumulate Across Vector Returning High 64 bits
ARM_vrmlaldavhX,          // Vector Rounding Multiply Add Long Dual Accumulate Across Vector Returning High 64 bits (exchange)
ARM_vrmlaldavhA,          // Vector Rounding Multiply Add Long Dual Accumulate Across Vector Returning High 64 bits (accumulate)
ARM_vrmlaldavhAX,         // Vector Rounding Multiply Add Long Dual Accumulate Across Vector Returning High 64 bits (accumulate, exchange)
ARM_vabav,                // Vector Absolute Difference and Accumulate Across Vector
ARM_vaddlv,               // Vector Add Long Across Vector
ARM_vaddlvA,              // Vector Add Long Across Vector (accumulate)
ARM_vaddv,                // Vector Add Across Vector
ARM_vaddvA,               // Vector Add Across Vector (accumulate)
ARM_vshlc,                // Whole Vector Left Shift with Carry
ARM_vmovlb,               // Vector Move Long Bottom
ARM_vmovlt,               // Vector Move Long Top
ARM_vcmla,                // Vector Complex Multiply Accumulate
ARM_vscclrm,              // Floating-point Secure Context Clear Multiple
ARM_vld20,                // Vector Deinterleaving Load - Stride 2 (pattern=0)
ARM_vld21,                // Vector Deinterleaving Load - Stride 2 (pattern=1)
ARM_vld40,                // Vector Deinterleaving Load - Stride 4 (pattern=0)
ARM_vld41,                // Vector Deinterleaving Load - Stride 4 (pattern=1)
ARM_vld42,                // Vector Deinterleaving Load - Stride 4 (pattern=2)
ARM_vld43,                // Vector Deinterleaving Load - Stride 4 (pattern=3)
ARM_vst20,                // Vector Interleaving Store - Stride 2 (pattern=0)
ARM_vst21,                // Vector Interleaving Store - Stride 2 (pattern=1)
ARM_vst40,                // Vector Interleaving Store - Stride 4 (pattern=0)
ARM_vst41,                // Vector Interleaving Store - Stride 4 (pattern=1)
ARM_vst42,                // Vector Interleaving Store - Stride 4 (pattern=2)
ARM_vst43,                // Vector Interleaving Store - Stride 4 (pattern=3)
ARM_vldrb,                // Vector Load Register/Vector Gather Load (byte)
ARM_vldrh,                // Vector Load Register/Vector Gather Load (halfword)
ARM_vldrw,                // Vector Load Register/Vector Gather Load (word)
ARM_vldrd,                // Vector Load Register/Vector Gather Load (doubleword)
ARM_vstrb,                // Vector Store Register/Vector Scatter Store (byte)
ARM_vstrh,                // Vector Store Register/Vector Scatter Store (halfword)
ARM_vstrw,                // Vector Store Register/Vector Scatter Store (word)
ARM_vstrd,                // Vector Store Register/Vector Scatter Store (doubleword)
ARM_vmov2,                // Vector Move (two general-purpose registers to two 32-bit vector lanes)
ARM_lsll,                 // Logical Shift Left Long
ARM_lsrl,                 // Logical Shift Right Long
ARM_asrl,                 // Arithmetic Shift Right Long
ARM_sqshll,               // Signed Saturating Shift Left Long
ARM_uqshll,               // Unsigned Saturating Shift Left Long
ARM_urshrl,               // Unsigned Rounding Shift Right Long
ARM_srshrl,               // Signed Rounding Shift Right Long
ARM_uqrshll,              // Unsigned Saturating Rounding Shift Left Long
ARM_sqrshrl,              // Signed Saturating Rounding Shift Right Long
ARM_sqrshr,               // Signed Saturating Rounding Shift Right
ARM_lctp,                 // Loop Clear with Tail Predication
ARM_vctp,                 // Create Vector Tail Predicate
// ARMv8.1-M PACBTI
ARM_pacbti,               // Pointer Authentication Code for the link register with BTI clearing, using key
ARM_autg,                 // Authenticate general value, using key
ARM_bxaut,                // Branch Exchange after Authenticating the address, using key
ARM_pacg,                 // Pointer Authentication Code for a general value, using key
// ARMv8.1-M RAS
ARM_esb,                  // Error Synchronization Barrier
// ARMv8.1-M Low Overhead Branch Extension
ARM_wls,                  // While Loop Start
ARM_dls,                  // Do Loop Start
ARM_wlstp,                // While Loop Start with Tail Predication
ARM_dlstp,                // Do Loop Start with Tail Predication
ARM_le1,                  // Loop End (count)
ARM_le2,                  // Loop End (forever)
ARM_letp,                 // Loop End with Tail Prediction
ARM_bf,                   // Branch Future
ARM_bfx,                  // Branch Future and Exchange
ARM_bfl,                  // Branch Future with Link
ARM_bflx,                 // Branch Future with Link and Exchange
ARM_bfcsel,               // Branch Future Conditional Select
// ARMv8-M Custom Datapath Extension
ARM_cx1,                  // Custom Instruction Class 1
ARM_cx1A,                 // Custom Instruction Class 1 (accumulator)
ARM_cx1d,                 // Custom Instruction Class 1 (pair)
ARM_cx1dA,                // Custom Instruction Class 1 (pair, accumulator)
ARM_cx2,                  // Custom Instruction Class 2
ARM_cx2A,                 // Custom Instruction Class 2 (accumulator)
ARM_cx2d,                 // Custom Instruction Class 2 (pair)
ARM_cx2dA,                // Custom Instruction Class 2 (pair, accumulator)
ARM_cx3,                  // Custom Instruction Class 3
ARM_cx3A,                 // Custom Instruction Class 3 (accumulator)
ARM_cx3d,                 // Custom Instruction Class 3 (pair)
ARM_cx3dA,                // Custom Instruction Class 3 (pair, accumulator)
ARM_vcx1,                 // Custom Extension Instruction Class 1
ARM_vcx1A,                // Custom Extension Instruction Class 1 (accumulator)
ARM_vcx2,                 // Custom Extension Instruction Class 2
ARM_vcx2A,                // Custom Extension Instruction Class 2 (accumulator)
ARM_vcx3,                 // Custom Extension Instruction Class 3
ARM_vcx3A,                // Custom Extension Instruction Class 3 (accumulator)
// FEAT_WFxT
ARM_wfet,                 // Wait For Event with Timeout
ARM_wfit,                 // Wait For Interrupt with Timeout
// FEAT_CSSC
ARM_ctz,                  // Count trailing zeros
ARM_rdvl,                 // Read multiple of vector register size to scalar register
ARM_rdsvl,                 // Read multiple of Streaming SVE vector register size to scalar register
// SVE integer binary arithmetic (predicated)
ARM_subr,                 // Reversed subtract vectors
ARM_addpt,                // Add checked pointer vectors (predicated)
ARM_subpt,                // Subtract checked pointer vectors (predicated)
ARM_sdivr,                // SVE Signed Divide Reversed
ARM_udivr,                // SVE Unsigned Divide Reversed
ARM_add_sve,              // Add (SVE)
ARM_sub_sve,              // Subtract (SVE)
ARM_mul_sve,              // Multiply (SVE)
ARM_smulh_sve,            // Signed Multiply High (SVE)
ARM_umulh_sve,            // Unsigned Multiply High (SVE)
ARM_sdiv_sve,             // Signed Divide (SVE)
ARM_udiv_sve,             // Unsigned Divide (SVE)
ARM_and_sve,              // Bitwise AND (SVE)
ARM_orr_sve,              // Bitwise OR (SVE)
ARM_eor_sve,              // Bitwise XOR (SVE)
ARM_bic_sve,              // Bitwise AND NOT (SVE)
ARM_smax_sve,             // Signed Maximum (SVE)
ARM_umax_sve,             // Unsigned Maximum (SVE)
ARM_smin_sve,             // Signed Minimum (SVE)
ARM_umin_sve,             // Unsigned Minimum (SVE)
ARM_sabd_sve,             // Signed Absolute Difference (SVE)
ARM_uabd_sve,             // Unsigned Absolute Difference (SVE)
ARM_subr_pred,            // Reversed subtract vectors (predicated)
// SVE bitwise shift (predicated)
ARM_asrd,                 // Arithmetic Shift Right for Divide
ARM_asrr,                 // Reversed Arithmetic Shift Right
ARM_lsrr,                 // Reversed Logical Shift Right
ARM_lslr,                 // Reversed Logical Shift Left
ARM_asr_sve,              // Arithmetic Shift Right (SVE)
ARM_lsr_sve,              // Logical Shift Right (SVE)
ARM_lsl_sve,              // Logical Shift Left (SVE)
ARM_sqshl_sve,            // Signed Saturating Shift Left (SVE)
ARM_uqshl_sve,            // Unsigned Saturating Shift Left (SVE)
ARM_sqshlu_sve,           // Signed Saturating Shift Left Unsigned (SVE)
ARM_srshr_sve,            // Signed Rounding Shift Right (SVE)
ARM_urshr_sve,            // Unsigned Rounding Shift Right (SVE)
// SVE integer multiply-add (predicated)
ARM_mla_sve,              // Multiply-Add (SVE)
ARM_mls_sve,              // Multiply-Subtract (SVE)
ARM_mad,                  // Multiply-Add writing multiplicand
ARM_msb,                  // Multiply-Subtract writing multiplicand
// SVE integer unary arithmetic (predicated)
ARM_cnot,                 // Logically invert boolean condition
ARM_sxtb_sve,             // Signed extend byte (SVE)
ARM_uxtb_sve,             // Unsigned extend byte (SVE)
ARM_sxth_sve,             // Signed extend halfword (SVE)
ARM_uxth_sve,             // Unsigned extend halfword (SVE)
ARM_sxtw_sve,             // Signed extend word (SVE)
ARM_uxtw_sve,             // Unsigned extend word (SVE)
ARM_neg_sve,              // Negate (SVE)
ARM_cls_sve,              // Count leading sign bits (SVE)
ARM_clz_sve,              // Count leading zeros (SVE)
ARM_not_sve,              // Bitwise NOT (SVE)
// SVE stack allocation
ARM_addvl,                // Add multiple of vector register size to scalar register
ARM_addpl,                // Add multiple of predicate register size to scalar register
// SVE index generation
ARM_index,                // Create index starting from and incremented by scalar/immediate
// SVE bitwise logical (unpredicated)
ARM_bsl1n,                // Bitwise Select with NOT (first source)
ARM_bsl2n,                // Bitwise Select with NOT (second source)
ARM_nbsl,                 // Bitwise Not-select
// SVE integer misc (unpredicated)
ARM_ftssel,               // Floating-point trigonometric select coefficient
ARM_fexpa,                // Floating-point exponential accelerator
// SVE element count
ARM_cntb,                 // Count elements (byte)
ARM_cnth,                 // Count elements (halfword)
ARM_cntw,                 // Count elements (word)
ARM_cntd,                 // Count elements (doubleword)
ARM_incb,                 // Increment scalar by element count (byte)
ARM_inch,                 // Increment by element count (halfword) [vector+scalar]
ARM_incw,                 // Increment by element count (word)
ARM_incd,                 // Increment by element count (doubleword)
ARM_decb,                 // Decrement scalar by element count (byte)
ARM_dech,                 // Decrement by element count (halfword) [vector+scalar]
ARM_decw,                 // Decrement by element count (word)
ARM_decd,                 // Decrement by element count (doubleword)
ARM_sqincb,               // Saturating signed increment (byte)
ARM_sqinch,               // Saturating signed increment (halfword)
ARM_sqincw,               // Saturating signed increment (word)
ARM_sqincd,               // Saturating signed increment (doubleword)
ARM_uqincb,               // Saturating unsigned increment (byte)
ARM_uqinch,               // Saturating unsigned increment (halfword)
ARM_uqincw,               // Saturating unsigned increment (word)
ARM_uqincd,               // Saturating unsigned increment (doubleword)
ARM_sqdecb,               // Saturating signed decrement (byte)
ARM_sqdech,               // Saturating signed decrement (halfword)
ARM_sqdecw,               // Saturating signed decrement (word)
ARM_sqdecd,               // Saturating signed decrement (doubleword)
ARM_uqdecb,               // Saturating unsigned decrement (byte)
ARM_uqdech,               // Saturating unsigned decrement (halfword)
ARM_uqdecw,               // Saturating unsigned decrement (word)
ARM_uqdecd,               // Saturating unsigned decrement (doubleword)
// SVE element count - 32-bit register (W) forms
ARM_sqincb32,             // Saturating signed increment byte, W-reg form
ARM_sqinch32,             // Saturating signed increment halfword, W-reg form
ARM_sqincw32,             // Saturating signed increment word, W-reg form
ARM_sqincd32,             // Saturating signed increment doubleword, W-reg form
ARM_uqincb32,             // Saturating unsigned increment byte, W-reg form
ARM_uqinch32,             // Saturating unsigned increment halfword, W-reg form
ARM_uqincw32,             // Saturating unsigned increment word, W-reg form
ARM_uqincd32,             // Saturating unsigned increment doubleword, W-reg form
ARM_sqdecb32,             // Saturating signed decrement byte, W-reg form
ARM_sqdech32,             // Saturating signed decrement halfword, W-reg form
ARM_sqdecw32,             // Saturating signed decrement word, W-reg form
ARM_sqdecd32,             // Saturating signed decrement doubleword, W-reg form
ARM_uqdecb32,             // Saturating unsigned decrement byte, W-reg form
ARM_uqdech32,             // Saturating unsigned decrement halfword, W-reg form
ARM_uqdecw32,             // Saturating unsigned decrement word, W-reg form
ARM_uqdecd32,             // Saturating unsigned decrement doubleword, W-reg form
// SVE Permute Vector - Extract
ARM_ext_sve_destr,        // Extract vector from pair of vectors (Destructive)
ARM_ext_sve_constr,       // Extract vector from pair of vectors (Constructive)
// SVE bitwise immediate
ARM_dupm,                 // Broadcast logical bitmask immediate to vector (unpredicated)
ARM_fdup,                 // Broadcast floating-point immediate to vector (unpredicated)
// SVE Integer Wide Immediate - Predicated
ARM_cpy_pred,             // Copy integer immediate to active elements (predicated)
ARM_fcpy_pred,            // Copy FP immediate to active elements (predicated)
// SVE Permute Vector - One Source Quadwords
ARM_dupq,                 // Broadcast indexed element in each quadword vector segment (unpredicated)
ARM_extq,                 // Extract vector segment from each pair of quadword vector segments
// SVE Permute Predicate
ARM_punpkhi,              // Unpack and widen high half of predicate
ARM_punpklo,              // Unpack and widen low half of predicate
// SVE Permute Vector - Predicated
ARM_compact,              // Compress active elements to lower-numbered elements
ARM_lasta,                // Extract element after last active to register
ARM_lastb,                // Extract last active element to register
ARM_clasta,               // Conditionally extract element after last (destructive)
ARM_clastb,               // Conditionally extract last element (destructive)
ARM_revb,                 // Reverse bytes within elements (predicated)
ARM_revh,                 // Reverse halfwords within elements (predicated)
ARM_revw,                 // Reverse words within elements (predicated)
ARM_revd,                 // Reverse doublewords within elements (predicated)
ARM_rbit_pred,            // Reverse bits within elements (predicated, SVE)
ARM_splice_destr,         // SPLICE destructive: select elements from first then second vector
ARM_splice_constr,        // SPLICE constructive (SVE2): select from pair {Zn, Zn+1}
ARM_sel_sve,              // SVE select vector elements (predicated)
// SVE Permute Vector - Unpredicated
ARM_insr,                 // Insert scalar register into shifted vector (unpredicated)
ARM_sunpkhi,              // Signed unpack and extend top half of vector
ARM_sunpklo,              // Signed unpack and extend bottom half of vector
ARM_uunpkhi,              // Unsigned unpack and extend top half of vector
ARM_uunpklo,              // Unsigned unpack and extend bottom half of vector
// SVE Integer Compare
ARM_cmp_sve,              // SVE integer compare (vectors and wide elements)
// SVE Partition Break
ARM_brka,                 // SVE partition break after
ARM_brkas,                // SVE partition break after, setting flags
ARM_brkb,                 // SVE partition break before
ARM_brkbs,                // SVE partition break before, setting flags
ARM_brkn,                 // SVE propagate break to next partition
ARM_brkns,                // SVE propagate break to next, setting flags
ARM_brkpa,                // SVE propagate break after from previous
ARM_brkpas,               // SVE propagate break after from previous, setting flags
ARM_brkpb,                // SVE propagate break before from previous
ARM_brkpbs,               // SVE propagate break before from previous, setting flags
// SVE Predicate Misc
ARM_ptest,                // SVE predicate test
ARM_pfirst,               // SVE predicate first active
ARM_pfalse,               // SVE predicate false
ARM_pnext,                // SVE predicate next active
ARM_rdffr,                // SVE read first-fault register
ARM_rdffrs,               // SVE read first-fault register, setting flags
ARM_ptrue,                // SVE predicate initialize
ARM_ptrues,               // SVE predicate initialize, setting flags
// SVE Predicate Logical
ARM_and_pred,             // SVE predicate AND
ARM_bic_pred,             // SVE predicate BIC
ARM_eor_pred,             // SVE predicate EOR
ARM_sel_pred,             // SVE predicate SEL
ARM_orr_pred,             // SVE predicate ORR
ARM_orn_pred,             // SVE predicate ORN
ARM_nor_pred,             // SVE predicate NOR
ARM_nand_pred,            // SVE predicate NAND
ARM_ands_pred,            // SVE predicate ANDS
ARM_bics_pred,            // SVE predicate BICS
ARM_eors_pred,            // SVE predicate EORS
ARM_orrs_pred,            // SVE predicate ORRS
ARM_orns_pred,            // SVE predicate ORNS
ARM_nors_pred,            // SVE predicate NORS
ARM_nands_pred,           // SVE predicate NANDS
// SVE Predicate Count
ARM_cntp,                 // SVE count active predicate elements
// SVE Inc/Dec by Predicate Count
ARM_sqincp,               // SVE saturating inc scalar/vector by predicate count
ARM_uqincp,               // SVE unsigned saturating inc scalar/vector by predicate count
ARM_sqdecp,               // SVE saturating dec scalar/vector by predicate count
ARM_uqdecp,               // SVE unsigned saturating dec scalar/vector by predicate count
ARM_incp,                 // SVE inc scalar/vector by predicate count
ARM_decp,                 // SVE dec scalar/vector by predicate count
// SVE Write FFR
ARM_wrffr,                // SVE write first-fault register
ARM_setffr,               // SVE set first-fault register
// SVE Integer Compare - Scalars
ARM_while,                // SVE while (condition in insn.cond)
ARM_while_cnt,            // SVE while predicate-as-counter (condition in insn.cond)
ARM_cterm,                // SVE conditionally terminate (condition in insn.cond)
ARM_whilewr,              // SVE while pointer conflict (write after read)
ARM_whilerw,              // SVE while pointer conflict (read after write)
// SVE Scalar Integer Compare - Predicate-as-counter
ARM_pext,                 // SVE predicate extract from predicate-as-counter
// SVE Integer Multiply-Add - Unpredicated
ARM_sqdmlalbt,            // SVE2 saturating multiply-add interleaved long (bottom*top)
ARM_sqdmlslbt,            // SVE2 saturating multiply-subtract interleaved long (bottom*top)
ARM_cdot,                 // SVE2 complex integer dot product
ARM_cmla,                 // SVE2 complex integer multiply-add
ARM_sqrdcmlah,            // SVE2 saturating rounding doubling complex multiply-add high
ARM_smlalb,               // SVE2 signed multiply-add long (bottom)
ARM_smlalt,               // SVE2 signed multiply-add long (top)
ARM_umlalb,               // SVE2 unsigned multiply-add long (bottom)
ARM_umlalt,               // SVE2 unsigned multiply-add long (top)
ARM_smlslb,               // SVE2 signed multiply-subtract long (bottom)
ARM_smlslt,               // SVE2 signed multiply-subtract long (top)
ARM_umlslb,               // SVE2 unsigned multiply-subtract long (bottom)
ARM_umlslt,               // SVE2 unsigned multiply-subtract long (top)
ARM_sqdmlalb,             // SVE2 saturating multiply-add long (bottom)
ARM_sqdmlalt,             // SVE2 saturating multiply-add long (top)
ARM_sqdmlslb,             // SVE2 saturating multiply-subtract long (bottom)
ARM_sqdmlslt,             // SVE2 saturating multiply-subtract long (top)
// SVE2 Integer - Predicated (C4.1.66)
// C4.1.66.3 saturating/rounding shift reversed
ARM_srshlr,               // Signed Rounding Shift Left Reversed
ARM_urshlr,               // Unsigned Rounding Shift Left Reversed
ARM_sqshlr,               // Signed Saturating Shift Left Reversed
ARM_uqshlr,               // Unsigned Saturating Shift Left Reversed
ARM_sqrshlr,              // Signed Saturating Rounding Shift Left Reversed
ARM_uqrshlr,              // Unsigned Saturating Rounding Shift Left Reversed
// C4.1.66.4 halving subtract reversed
ARM_shsubr,               // Signed Halving Subtract Reversed
ARM_uhsubr,               // Unsigned Halving Subtract Reversed
// C4.1.66.6 saturating subtract reversed
ARM_sqsubr,               // Signed Saturating Subtract Reversed
ARM_uqsubr,               // Unsigned Saturating Subtract Reversed
// C4.1.66.3 saturating/rounding shift (SVE predicated)
ARM_srshl_sve,            // Signed Rounding Shift Left (SVE)
ARM_urshl_sve,            // Unsigned Rounding Shift Left (SVE)
ARM_sqrshl_sve,           // Signed Saturating Rounding Shift Left (SVE)
ARM_uqrshl_sve,           // Unsigned Saturating Rounding Shift Left (SVE)
// C4.1.66.4 halving add/subtract (SVE predicated)
ARM_shadd_sve,            // Signed Halving Add (SVE)
ARM_uhadd_sve,            // Unsigned Halving Add (SVE)
ARM_shsub_sve,            // Signed Halving Subtract (SVE)
ARM_uhsub_sve,            // Unsigned Halving Subtract (SVE)