Get to market faster with an error-free system memory map
Overview
Accelerate large-scale SoCs schedules with effective hardware/software interface development
Magillem® Registers offers a single source of truth methodology, which not only targets the traditional need to manage registers, but also addresses today’s hardware and software integration challenges for large-scale SoCs.
Quick and scalable automated implementation with Magillem Registers helps cut time to market in half for hardware/software interface (HSI) generation.
Straightforward register intent capture
Magillem Registers translates register specifications into executable design code by automatically importing the register descriptions from different sources and formats.
- Automatically checks the accuracy of the information (overlaps, configurability, reserved empty spaces, …).
- Enables close collaboration between hardware, software, and tech doc teams through a single source of truth methodology for consistently generated data.
- Comprehensive HSI automation helps ensure improved quality design and increased productivity.
Automatically generate consistent data
Magillem Registers is a true cross-compiler with over 1,000 functional, behavioral, syntactic, and semantic error checks. It supports various formats and generates multiple outputs simultaneously.
Generated data is consistent and complete, which gives verification teams an up-to-date generated register model to work from.
Error-free system map generation
Full Magillem Registers and Magillem Connectivity integration synchronizes connectivity and memory map information:
- Calculate and display the system map from the selected initiator.
- Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
- Check that all the software visible elements (registers or memory regions) in connected targets are present in the memory map.
Features
Magillem Registers key features
Full NoC integration for automated flow
Leverage SoC connectivity information:
- Increase productivity with reduced process.
- Improve quality with early error detection by checkers.
Benefits
Magillem Registers product benefits
Magillem Platform
Powerful comprehensive SoC integration automation
| Category | Features | Magillem Packaging | Magillem Connectivity | Magillem Registers |
|---|---|---|---|---|
| IP-XACT Conversion | 2009 to 2022 | |||
| 2014 to 2022 | ||||
| Resource Management | Projects | |||
| Catalogs | ||||
| Components | ||||
| TGI | TGI API | |||
| HDL Import | Verilog/SystemVerilog support | |||
| View & FileSet elaboration | ||||
| Bus Interface | Auto mapping | |||
| Rules Checkers | Design and component | |||
| Memory and system map | ||||
| Configurable checker severity | ||||
| Assembly | Rule-based connectivity | |||
| Bus/signal split/tie/open/feedthrough | ||||
| Glue logic insertion | ||||
| RTL Netlist Generation | Configurable header | |||
| Keep parameter expressions | ||||
| Signals/netname/tie management | ||||
| Hierarchical Manipulations | Merge, Flatten, Move operations | |||
| Parameter propagation | ||||
| IP Update | Rename/resize/delete/merge | |||
| User mapping rules definition | ||||
| Diff and Merge | Accept/Reject any change | |||
| Conflict resolution wizard | ||||
| Import Memory Map Description | SystemRDL support | |||
| IP-XACT support | ||||
| Excel spreadsheets support | ||||
| Generate HSI Outputs | RTL register bank (VHDL, Verilog, SystemVerilog) | |||
| Customized C Header files | ||||
| UVM RAL files | ||||
| Documentation (Word, FrameMaker, HTML) | ||||
| SystemRDL description | ||||
| IP-XACT description |
Resources